Abstract: A temperature control device includes: a top plate that supports a substrate; a base plate connected to the top plate so as to form an internal space with the top plate; a thermoelectric module plate arranged in the internal space; a heat exchange plate that is arranged in the internal space and exchanges heat with the thermoelectric module plate; a first coupling member that couples the top plate and the base plate via the thermoelectric module plate and the heat exchange plate and is fixed to each of the top plate and the base plate; and a second coupling member that couples the top plate and the base plate via the thermoelectric module plate and the heat exchange plate, is fixed to the top plate, and is movable relative to the base plate.

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Abstract: Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.

Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.

Abstract: A probe pin inspection mechanism a includes a base, a pair of movable bodies, a pair of movable-body elastic bodies, and a conductor. The movable bodies are supported by the base to be movable in a first direction from a first position with respect to the base, and respectively include ends and terminals electrically connected to the respective ends. The movable-body elastic bodies elastically press the movable bodies in a second direction. The conductor is supported by the base and electrically connects the terminals of the movable bodies by making contact with the terminals. The state between the terminals and the conductor is switched, according to the position of the movable bodies, between a conductive state in which the terminals and the conductor are in contact with each other and a non-conductive state in which the terminals and the conductor are separated from each other.

Abstract: A connecting device for electrically connecting signal contact portions of an electrical device under test includes a lower modular unit and an upper modular unit. The lower modular unit includes a port substrate and a plurality of lower connecting terminals electrically connected with the port substrate. The upper modular unit is disposed above the lower modular unit and includes a plurality of upper connecting terminals movable relative to an upper wall. The upper connecting terminals are movable as a result of a downward pressing of the electrical device to the upper modular unit to project outwardly of the upper wall and to electrically connect with the signal contact portions. The upper connecting terminals are electrically connected with the lower connecting terminals.

Abstract: Disclosed in the present specification are an apparatus and a method capable of quickly verifying a plurality of micro LEDs. An LED verification substrate according to the present specification is a micro LED verification substrate having a plurality of verification chips, wherein each verification chip can comprise: a first contact deposited on the upper side of a lower substrate; a first passivation layer deposited on the upper side of the first contact; a second contact deposited on the upper side of the first passivation layer; a second passivation layer deposited on the upper side of the second contact; a first bump electrically connected to the first contact and protruding above the upper surface of the second passivation layer; and a second bump electrically connected to the second contact and protruding above the upper surface of the second passivation layer.

Abstract: An electrical connecting device includes a probe head, and probes for measurement and probes for confirmation held by the probe head. The probe head holds the probes for measurement and the probes for confirmation in a state in which the respective tip ends are exposed therefrom. An exposed length from the probe head to the tip end is shorter for the probes for confirmation than for the probes for measurement.

Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Abstract: The present invention provides a probe apparatus, which comprises a signal transmission device, a probe, and a bottom fixing device. The signal transmission device includes a first transmission part and a second transmission part. An end of the probe is connected electrically below the second transmission part. The bottom fixing device is disposed below the signal transmission device. An end of the bottom fixing device includes a first penetrating hole and a first recess is disposed below the end. The probe passes through the first penetrating hole of the bottom fixing device. The probe is located in the first recess. The bottom fixing device reinforces the mechanical strength of the signal transmission device so that the width of the signal transmission device can be reduced. Thereby, the benefit of high-density arrangement of the probe apparatus can be achieved.

Abstract: An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.

Abstract: A method is provided for in situ functionality testing of electrical switches using a Functional Reflectometry Test (FRT) of switches on the signal path of electrical circuits in a semiconductor interface. The method includes initiating the functionality testing of the electrical switches in situ, wherein the functionality of the electrical switches is tested while the electrical switches are connected to the Automatic Test Equipment (ATE) and are in-use testing semiconductors. The method also includes conducting full Functional Reflectometry Testing of the electrical switches in situ in an open switch state and a closed switch state to determine whether each of the electrical switches is one of fully functional, stuck closed, and stuck open, wherein testing for each state is performed as a single vector functional test to minimize test time overhead.

Abstract: A temporary bond method and apparatus for allowing wafers, chips or chiplets. To be tested, the temporary bond method and apparatus comprising: a temporary connection apparatus having one of more knife-edged microstructures, wherein the temporary connection apparatus serves, in use, as a probe device for probing the chiplets, each chiplet including a die having one or more flat contact pads which mate with the one of more knife-edged microstructures of the temporary connection apparatus; a press apparatus for applying pressure between the one or more flat contact pads on the chiplet with the one of more knife-edged microstructures of the temporary connection apparatus thereby forming a temporary bond between the temporary connection pad with the knife-edged microstructure in contact with the one or more flat wafer pads; the press being able to apply a pressure to maintain the temporary bond connection during or prior to testing of the chiplet.

Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

Abstract: A test board includes a board substrate, a connector at a side of the board substrate, a plurality of device-under-test (DUT) boards which are connected to the board substrate and on which semiconductor devices are mounted as DUTs, and a plurality of DC-DC converters connected to the plurality of DUT boards. The plurality of DC-DC converters convert an input voltage supplied thereto via the connector into operating voltages, and provide the operating voltages to the semiconductor devices on the plurality of DUT boards corresponding thereto. The operating voltages are substantially the same.

Abstract: A test board and a test apparatus having the same are disclosed. The test board includes a base plate including a connector and a plurality of mounting areas in a matrix shape having a mounting row in a first direction and a mounting column in a second direction, a plurality of test units arranged on the mounting areas of the base plate and a test object is mounted in each of the mounting areas, and a fluid supplier disposed on the base plate and supplying a test fluid to each of the test units having a test temperature and a supplementary fluid to the test object to reduce a temperature difference between an actual temperature of the test object and the test temperature such that the actual temperature of the test objects is substantially below the test temperature.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

Abstract: The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor.

Abstract: Methods, systems, and apparatus for electrical connector assemblies. The assemblies include a socket defining a signal cavity, the socket having a first socket opening and a second socket opening. The assemblies include a signal contact probe located within the signal cavity. The signal contact probe includes a first plunger received in the shell cavity and extending through a first shell opening and located in the first socket opening. The signal contact probe includes a second plunger received in the shell cavity and extending through a second shell opening and located in the second socket opening. The assemblies include an end insulation ring located in the second socket opening and around the second plunger, the end insulation ring configured to facilitate substantially constant impedance through the signal spring probe, and configured to restrict lateral movement of the second plunger within the second socket opening.

Abstract: A test system configured to perform an electrical-characteristic test on a device under test, includes: a mount on which the device under test is to be mounted; a conveyance mechanism configured to convey the mount; a test head including a measurement circuit for performing the electrical-characteristic test; a probe configured to connect an electrode of the device under test to the measurement circuit; a lifting and lowering mechanism configured to move the mount along a first direction such that the electrode and the probe are in contact or spaced apart; and an alignment mechanism provided at the test head, the alignment mechanism being configured to move the probe on a plane crossing the first direction so as to align the probe with the electrode on the plane.

Abstract: A system for controlling delivery of power to a load includes a master control unit (MCU) and a synchronous solid-state relay. The MCU causes the relay to close when the voltage delivered to the relay is at a zero crossing state. The MCU causes the relay to open at either (a) the moment when the voltage delivered to the relay is at a zero crossing state, or (b) the moment that the current delivered to the relay is both over a threshold level and at a zero crossing state.

Abstract: An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.

Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

Abstract: In some embodiments, an apparatus includes an automatic integrated circuit (IC) handler having a change kit. The change kit has a plunger moveably disposable onto an automatic test equipment (ATE). In such embodiments, the ATE is configured to receive an integrated circuit having an optical interface. The plunger has a first position and a second position. In such embodiments, the plunger is out of contact with the integrated circuit when the plunger is in the first position. The plunger includes an optical connector operatively coupled to the optical interface of the integrated circuit when the plunger is in the second position.

Abstract: A connector is connectable with a conductive core of a cable which is inserted from a front of the connector along a front-rear direction. The connector comprises a shell and a spring member. The shell is made of a metal. The shell has an operation portion and a contact portion. The spring member is made of another metal which is harder than the metal of the shell. The spring member has an operated portion and a press portion. When the operation portion moves the operated portion, the press portion is moved away from the contact portion. The press portion presses the conductive core against the contact portion under a connection state where the conductive core is connected with the connector.

Abstract: A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device.

Abstract: An automated test platform for testing a first device under test includes N voltage sources for providing N different voltages. A cross matrix switching system is coupled to the N voltage sources, the cross matrix switch being configured to provide the N different voltages to M discrete test points within the first device under test, wherein M is larger than N. An N voltage measuring system is coupled to the first device under test, the N voltage measuring system being configured to measure the voltage potential present on the M discrete test points.

Abstract: A wafer inspection apparatus 10 includes a middle plate 22 that mounts a probe card 18 in which multiple contact probes 20 are provided; a drawer type table 21 in which the middle plate 22 is provided; a tester 15 to which the probe card 18 is mounted; and a transfer robot 17 that transfers the middle plate 22. The middle plate 22 includes a base 23 and multiple supports 24 protruding toward the probe card 18 to be mounted. A protruding height of each support 24 is equal to or higher than a protruding length of the contact probe 20 from the probe card 18. The probe card 18 is fastened to a probe card cover 29 when the probe card 18 is mounted on the middle plate 22, and the transfer robot 17 transfers the middle plate 22 from the table 21 to the tester 15.

Abstract: Methods are described for measuring data in a test setup including an impedance tuner. In an exemplary embodiment, the data is data for measuring noise parameters. The data is measured versus a sweep parameter for one tuner state at a time.

Abstract: A method and an apparatus for testing a display panel are provided. The apparatus comprises an interface circuit for connecting to the display panel to be tested, and a test circuit for generating a test signal to the display panel through the interface circuit in a test state for a display panel, and for generating an adjustment signal to the display panel through the interface circuit in a predetermined state for the display panel, wherein at least a portion of an afterimage signal in the display panel is reduced by the adjustment signal.

Abstract: The present invention discloses a probe frame for an array substrate detecting apparatus, the probe frame including a frame body and a signal distribution circuit board provided to the frame body, wherein the probe frame further includes: a circuit board provided to the frame body, the circuit board being provided with through holes, and the circuit board being provided therein with a plurality of signal transmission wires in a one to one correspondence with the through holes, one end of each signal transmission wire is inserted into its respective through hole and the other end thereof is electrically connected with an output end of the signal distribution circuit board; and a plurality of probes in a one to one correspondence with the through holes, wherein for each pair of the probe and the through hole, one end of the probe is inserted into the through hole so as to be electrically connected with the signal transmission wire within the through hole.

Abstract: An electrical connection assembly is disclosed. The electrical connection assembly includes a first circuit board and a second circuit board. The first circuit board has a plurality of first signal electrodes and at least one first test electrode, wherein the first signal electrodes and the first test electrode are arranged in a spaced manner on the same side of the first circuit board. The second circuit board has a plurality of second signal electrodes and at least one second test electrode, wherein the second signal electrodes and the second test electrode are arranged in a spaced manner on the same side of the second circuit board, wherein the first signal electrodes are electrically connected to the second signal electrodes and the first test electrode is electrically connected to the second test electrode to form a testing loop.

Abstract: A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (TSV) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the TSV so as to determine the presence or absence of metal pollution caused by the TSV.

Abstract: A supporting member separation apparatus that separates a supporting member from a laminate having a substrate, an adhesive layer, a release layer which has a property that changes when it absorbs light, and the supporting member which are laminated in this order. The apparatus includes a holding unit that holds one surface of the laminate, a lifting and lowering unit that lifts and lowers the holding unit, and an adjustment unit that maintains a constant applied force to the holding unit.

Abstract: The test board includes at least one first interface configured to electrically connect the test board with a test controller, at least one second interface configured to electrically connect the test board with at least one electrical device to be tested, respectively. The test board further includes at least one electrical component, and a bus system electrically connected to the first interface and one or more of the second interface and the electrical component.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: Multi-stage in circuit test of a circuit board has support to reduce strain placed on the circuit board during each test stage. A shuttle plate is disposed between a load plate that supports a circuit board under test and a probe plate that directs test probes towards the circuit board. The shuttle board slides between different positions with each position establishing the distance between the circuit board and the test probes. For instance, in a first position, the shuttle plate aligns intermediary members to rest between the load plate and shuttle plate to keep the probes spaced by a first distance from the circuit board so that only some test probes contact the circuit board. In a second position, the shuttle plate aligns the intermediary members with blind vias to bring the shuttle plate and load plate proximate each other so that all test probes contact the circuit board.

Abstract: Various embodiments for detecting a high Intensity radiated field (HIRF) in a line replaceable unit are provided. In an embodiment, the internal detector comprises a receiving means for receiving HIRF and generating an AC signal proportional to the HIRF, an RF filter configured to sample the AC signal to create a DC signal; and a detecting section configured to compare the DC signal with a threshold and output a result of the comparison to a built-in test section. The internal detector may be used to test EMI filter pin connectors of a closed line replaceable unit.

Abstract: A probe apparatus and method of terminating a probe that probes a semiconductor device with a signal cable from a tester site by site at a proximal end of the probe and a distal end of the signal cable. in one embodiment, the probe apparatus includes: a chassis; a dielectric block mounted in the chassis for retaining the probe, the probe extending on the chassis from a proximal end of the probe to the dielectric block, extending through the dielectric block, and projecting from the dielectric block towards the semiconductor device at a distal end of the probe; and a terminating apparatus, mounted in the chassis, for terminating the proximal end of the probe with a distal end of the signal cable side by side.

Abstract: A wiring board for an electronic parts inspecting device that can be designed and produced relatively quickly, inexpensively, and with a few number of jigs is provided. In certain embodiments the wiring board comprises a board main body having a front surface, a probe pad area having probe pads located in a central portion of the front surface, an outer connecting terminal area having outer connecting terminals located in a peripheral portion of the front surface, and wherein probe pads are connected to outer connecting terminals by front surface wirings formed between the probe pad area and the outer connecting terminal area. While certain embodiments further comprise inner wirings and first via conductors to connect the probe pads and outer connecting terminals, it is preferable to have no or a minimal amount of such inner wirings. Lastly, a method of manufacturing the same is provided.

Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

Abstract: A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: A test carrier 10A comprises: a base board 21A which holds a die 90; and a cover board 31A which is laid over the base board 21A so as to cover the die 90. The test carrier 10A comprises a seal member 24 which is interposed between the base board 21A and the cover board 31A and which surrounds the die 90.

Abstract: A circuit board includes a main part on which a processor is mounted, a cut part to be cut off from the main part at a cut section before the board is reused, and a conductor pattern wired through the cut part via the cut section and to be cut off into a plurality of patterns at the cut section as the cut part is cut off. The processor detects a difference in signal level between a level of a signal output from the conductor pattern before the cut part is cut off, and a level of the signal output from the conductor pattern after the cut part is cut off, to determine a number of times the board is reused.

Abstract: A test carrier which can suppress the occurrence of contact defects while securing positional precision of the terminals is provided. A test carrier 10 comprises: a base film 40 which has one main surface which has bumps which contact electrodes 91 of the die 90; and a cover film 70 which is laid over the base film 40, the die 90 is held between the base film 40 and the cover film 70, the base film 40 has: a first region 40a which has a first thickness t1; and a second region 40b which has a second thickness t2 which is thinner than the first thickness t1, and the second region 40b faces at least a part of the edge 92 of the die 90.

Abstract: A board for a probe card includes a ceramic board including a first insulating layer, and second insulating layers disposed on one surface of the first insulating layer and including cavities for receiving electronic components, conductive patterns disposed on the first and second insulating layers, conductive vias electrically connecting the conductive patterns, and a capacitor disposed in the cavities. The cavities have a depth greater than a thickness of the capacitor to secure a space in a lower portion of the cavity after receiving the capacitor.