Abstract: A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.

Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

Abstract: A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.

Abstract: A service life testing device for a pressure sensor includes a first and a second plates, the first plate including a stage carrying a to-be-tested pressure sensor; a pair of drivers, two ends thereof respectively connected to the first and the second plates; a pair of linear slide mechanisms, disposed between the first and the second plates, and each including a slide rail and a slider moving there along, where a compression spring is disposed along an axial direction of each slide rail; a jig, disposed between the first and the second plates, and facing the to-be-tested pressure sensor; and a processing unit, electrically connected to the drivers and the to-be-tested pressure sensor, and configured to control a moving direction, a moving speed, and a moving stroke of the drivers, to cause the to-be-tested pressure sensor to press against or move away from a surface of the jig.

Abstract: In a mounting system including multiple mounting machines, there is provided a mounting system that is capable of reducing the number of measurement devices that measure electrical characteristics of an electronic component. A control device controls a switching device in order to connect a measurement device and a mounting machine that transmitted request information for measuring the electrical characteristics of the electronic component. When transmitting an instruction for starting measurement to the measurement device and receiving a characteristic measurement value from the measurement device, the control device transfers the received characteristic measurement value to the mounting machine that transmitted request information.

Abstract: The systems, apparatuses, and methods herein can provide a multi-site positioning mechanism suitable for long-term testing of a device(s) under test (DUT) (e.g. semiconductor wafers) across a range of temperatures with or without a controlled environment. The systems, apparatuses, and methods herein include mounting components, mechanisms, and structures that can provide excellent mechanical stability, permit relatively close working distance optics with high resolution, enable fine positioning at elevated temperature in a controlled environment with minimal thermal perturbation. The systems, apparatuses, and methods herein can be provided with modularity, for example as modular with rails and test sites that can be easily added or removed, and that can permit access to probe modules in a densely packed array.

Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

Abstract: An apparatus for testing a package-on-package semiconductor device comprises a pick and place device for loading a first chip into or unloading the first chip from a test socket and a lifting and rotating arm for moving a chip placement module which receives a second chip to a position between the pick and place device and the test socket. The pick and place device and the chip placement module are lowered, and then a test process is performed. After the test process is completed, the pick and place device and the chip placement module are lifted, and the lifting and rotating arm moves the chip placement module to one side of the pick and place device. Accordingly, a method for testing the semiconductor device could be performed automatically so as to greatly enhance test efficiency and accuracy and to significantly reduce costs.

Abstract: Damage to conductive material that serves as bridging connections between conductive structures within an electronic device may result in deficiencies in radio-frequency (RF) and other wireless communications. A test system for testing device structures under test is provided. Device structures under test may include substrates and a conductive material between the substrates. The test system may include a test fixture for increasing tensile or compressive stress on the device structures under test to evaluate the resilience of the conductive material. The test system may also include a test unit for transmitting RF test signals and receiving test data from the device structures under test. The received test data may include scattered parameter measurements from the device structures under test that may be used to determine if the device structures under test meet desired RF performance criteria.

Abstract: A test system for testing a device under test (DUT) is provided. The test system may include a DUT receiving structure configured to receive the DUT during testing and a DUT retention structure that is configured to press the DUT against the DUT receiving structure so that DUT cannot inadvertently shift around during testing. The DUT retention structure may include a pressure sensor operable to detect an amount of pressure that is applied to the DUT. The DUT retention structure may be raised and lowered vertically using a manually-controlled or a computer-controlled positioner. The positioner may be adjusted using a coarse tuning knob and a fine tuning knob. The positioner may be calibrated such that the DUT retention structure applies a sufficient amount of pressure on the DUT during production testing.

Abstract: A method of testing objects and an apparatus for performing the same, the method including loading the objects into a testing unit through a loading unit; testing the objects in the testing unit and determining whether the objects are normal objects or abnormal objects; unloading the tested objects from the testing unit to an unloading unit; directly reversely loading the abnormal objects from the unloading unit into the testing unit when the objects are determined to be abnormal objects; and re-testing the abnormal objects in the testing unit.

Abstract: An align fixture for aligning an electronic component having a receptacle adapted to receive the electronic component and having a first abutting section and a second abutting section, the first abutting section being mounted via an elastic unit, the first abutting section and the second abutting section delimit an electronic component receiving volume in which the electronic component is to be received in the receptacle, the elastic unit extends below a bottom side of the electronic component receiving volume, and the elastic unit is adapted to provide a clamping force for clamping the electronic component between the first abutting section and the second abutting section.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.

Abstract: Testing stacked devices. In accordance with a first method embodiment, a primary circuit assembly is accessed from a first circuit assembly carrier. The primary circuit assembly is placed into a test fixture. A secondary circuit assembly is accessed from a second circuit assembly carrier. The secondary circuit assembly is placed into the test fixture on top of the primary circuit assembly. The primary circuit assembly is tested in conjunction with said secondary circuit assembly while coupled together.

Abstract: [Problem] A test carrier able to secure a high air-tightness is provided. [Solution] A test carrier 10 comprises a cover member 50A and a base member 20A which are bonded together while sandwiching a die 90 between them. ultraviolet rays can pass through the cover member 50A.

Abstract: An apparatus for testing a semiconductor package including a shuttle, a socket and a pressing unit may be provided. The shuttle may include a pocket, which is configured to receive the semiconductor package and a printed circuit board (PCB). The PCB may be configured to make electrical contact with the semiconductor package. The socket may be arranged under the shuttle and include socket pins configured to make electrical contact with the PCB. The pressing unit may be arranged on the shuttle and may be movable in a vertical direction. The pressing unit may press on the shuttle toward the socket such that the semiconductor package may be electrically connected to the socket pins. Because the semiconductor package received in the shuttle may make contact with the socket at the testing region to test the semiconductor package, the semiconductor package may not fall off or may not be slanted.

Abstract: The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-

Abstract: A system for monitoring a die connection includes a die bonded to a substrate and a connection indicator circuit coupled to a monitor pad of the die. The connection indicator circuit is configured to detect a connection failure of the monitor pad. A signal corresponding to the monitor pad of the die is monitored, and an indication of a pad connection failure associated with the monitor pad is provided in response to a change in the monitored signal.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 ?m. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.

Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package.

Abstract: A semiconductor chip test method used in a semiconductor chip test apparatus including an electric energy measurement unit defining multiple conducting pin holes in a recess of an electric energy test table for holding contact pins of a semiconductor chip for testing electric properties, a functional tester disposed adjacent to the electric energy measurement unit for testing predetermined functions of the semiconductor chip in a functional test table thereof and transmitting tested data to an external display screen through a display card, and a conveyer unit controllable to deliver the test semiconductor chip to the electric energy test table for electric energy measurement and to the functional test table of the functional tester for functional test.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

Abstract: An opener for a test handler is provided. Even when holding members of inserts of a carrier board are manipulated to release semiconductor devices that have been in a held state, a predetermined distance can remain between an upper surface of the opening plate and a lower surface of the insert, thus preventing the inserts from becoming defective.

Abstract: A test device for testing a solar module includes a transfer unit for transporting the solar module through the test device, an irradiation unit for irradiating the solar module, an imaging unit for optically capturing an image of the solar module and a tapping device for sensing parameters of the solar module and/or for supplying voltage to the solar module. The tapping device includes a contact bar on which a contact surface positioned on the solar module can glide or slide along during the transport process in order to generate an electrical connection. The contact surface is provided by a contact device that can be temporarily attached to the solar module.

Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.

Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.

Abstract: A first semiconductor tier has a first tier-to-tier connector for detecting a tier-to-tier coupling in a stacked integrated circuit (IC) device. A second semiconductor tier has a second tier-to-tier connector configured to electrically couple to the first tier-to-tier connector. A tier-to-tier detection circuit electrically couples to the second tier-to-tier connector. The tier-to-tier detection circuit generates an output signal indicative of an electrical coupling between the first semiconductor tier and the second semiconductor tier.

Abstract: An electronic device test fixture deploys a plurality of contact elements in a dielectric housing. The plumb arrangement of contact elements each include an armature or transversal configured to first depress and then slide laterally when urged downward by the external contacts of a device under test. The rotary movement of the transversal is optimized via the configuration of a surrounding forked regulator such that surface oxide deposition on the external device under test terminal is disrupted to reliably minimize contact resistance without damaging or unduly stressing the electrical junction of the device under test.

Abstract: A system separating defective dies from a wafer comprises a film frame platform and a pick-and-place device. The film frame platform comprises a support table assembly configured for supporting a film frame assembly and a platform surface configured to receive the placement of bins thereupon. The pick-and-place device is configured for moving in a linear manner between the support table assembly and the platform surface.

Abstract: An improved method and apparatus for testing and sorting electro-optic devices by both electrical and optical properties at high speed is disclosed. Electro-optic devices, in particular light emitting diodes, are singulated by a singulation device and transferred to a linear track where they are tested for electrical and optical properties. The devices are then sorted into a large number of different bins depending upon the tested properties.

Abstract: Provided are apparatus and method of testing solid state drives. The method includes accommodating solid state drives to be tested in a magazine with one or more cassettes, sorting the solid state drives into operable solid state drives or defective solid state drives by testing electrical characteristics, and loading the sorted solid state drives.

Abstract: A method of testing semiconductor devices, the method includes the steps of making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical connections to a second set of devices to allow a second set of tests to be performed on the second set of devices, wherein the first and second sets of tests are different, and concurrently performing the first set of tests on the first set of devices and the second set of tests on the second set of devices.

Abstract: A test tray for a test handler is disclosed that is loaded with semiconductor devices and then carries them along a predetermined circulation route. The test tray allows one fixing unit to fix a plurality of adjacent insert modules to the receiving spaces of the frame, thereby efficiently using the space of the frame and allowing a relatively large number of insert modules to be installed in the same area, in comparison to the conventional test tray.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: An electronic component pressing device includes a first pressing member for pressing a predetermined first region of the electronic component to be tested; a second pressing member for pressing a predetermined second region other than the first region of the electronic component to be tested; a gimbal mechanism for adhering the first pressing member to the first region when the first pressing member presses the first region of the electronic component to be tested; first pressing load applying means for applying a pressing load on the gimbal mechanism; and second pressing load applying means for applying a pressing load on the second pressing member.

Abstract: A test handler and method for operating a test handler for testing semiconductor devices are provided. The test handler includes a test tray located on one side of an opening apparatus in which a plurality of inserts are arrayed, wherein each insert comprises at least one semiconductor device loaded thereon, at least one opening unit for opening inserts at one part of the one side of the test tray, and a position changing apparatus comprises a motor including a driving pulley for moving at least one opening unit along a contact surface of the test tray such that the at least one opening unit changes positions on the test tray and is located at another part of the one side of the test tray in order to open inserts at the other part of the one side of the test tray.

Abstract: A test handler for a semiconductor package includes a loader unit that is configured to transfer the semiconductor package to a test tray. A test chamber is configured to test the semiconductor package loaded in the test tray. An unloader unit is configured to remove the tested semiconductor package from the test tray. A loader stage is configured to convey the test tray from the unloader unit to the loader unit. A test tray cleaning unit proximate the loader stage is configured to clean the test tray while it is being conveyed from the unloader unit to the loader unit.

Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.

Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: An electronic device test apparatus which can optimize throughput and costs is provided. An electronic device test apparatus 1 comprises: a test cell cluster 10 having cell groups 11A to 11H each of which has a plurality of test cells 20; and a conveyor apparatus 30 supplying test carriers to a plurality of the test cells 20, and each of the test cell 20 has: contactors 215; a flow path 221 connected to a vacuum pump 25 and reducing pressure in a recess 211 of a pocket 21 so as to bring external terminals 73 and the contactors 215 into contact; and a test circuit for running a test on an electronic circuit formed into a die 90.

Abstract: A test handler is disclosed in the present invention. The test handler may include a test tray on which a plurality of inserts are arrayed for loading at least one semiconductor device, at least one opening unit for simultaneously opening one part of the plurality of inserts which are arrayed on one part of the test tray, and a test tray transfer apparatus for allowing the opening unit to simultaneously open other parts of the plurality of inserts which are arrayed on another part of the test tray as the test tray is transferred. Therefore, although semiconductor devices to be tested change their sizes, the replaced parts of the test handler are reduced in number, thereby reducing manufacturing cost and replacement work time. The inventive test handler reduces semiconductor devices loading time, reduces jamming, increases teaching efficiency and improves space utilization efficiency. Furthermore, the test handler can be applied to various types of testers.