Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.

Abstract: A logic signal analyzer for analyzing logic signals has a positive measurement input providing a positive measurement input voltage value, a negative measurement input providing a negative measurement input voltage value, a third input providing a third input voltage value, and a comparison unit. The comparison unit being configured to provide a first and a second comparison output voltage value each based on one of at least four comparison modes. The first and second comparison output values are based on different comparison modes.

Abstract: An automated test equipment includes a test processor configured to provide a signal to a device under test on the basis of a sequence of instructions defining an evaluation of test vectors. The test processor is configured to map a test vector onto a set of signal states or signal transitions. Furthermore, the test processor is configured to variably select a number of signal states or signal transitions provided in the signal based on a current test vector in dependence on a current instruction.

Abstract: An improved testing assessment tool and methodology maps the Testing Maturity Model (TMM) structure to individual test areas, thereby enabling comprehensive and targeted improvement. In this way, the present invention uses the five TMM maturity levels to assess individual areas, rather than merely assigning a single maturity level to the entire organization. Embodiments of the present invention include a quick assessment that includes a relatively small number of questions to be subjectively answered using the TMM hierarchy. Embodiments of the present invention further include a full assessment that includes a relatively large number of questions to be discretely answered, with these results being use to evaluate various testing areas using the TMM hierarchy.

Abstract: There is provided an apparatus for sensing an arc in a gas insulated switchgear (GIS) including: an optical signal receiving unit receiving an optical signal generated due to an arc within a GIS; and a circuit breaker controller outputting a circuit breaker interrupt signal based on the received optical signal, wherein the optical signal receiving unit is installed within the GIS. An optical signal due to an arc may be received at the maximum level, and an arc generated within a GIS may be simply sensed at low costs.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. The data can then be interpreted in the grammar system or used as input to a fault isolation engine to determine anomalies in the system under test. Based on identified faults, one or more mitigation techniques may be implemented in an automated fashion.

Abstract: There is provided a glass substrate for electronic amplification having through holes formed on a plate-like glass member and used for causing an electron avalanche in the through holes, wherein a shape of the glass substrate for electronic amplification and a material of the glass member are determined so that an insulation resistance in a plate thickness direction per plane of 100 cm2 is 107 to 1011?.

Abstract: Electronic circuits and methods are provided for use in hot-swappable circuit board applications. Circuitry detects an electrical ground connection and signals operation of a hot-swap controller. Detection of stable operating power causes a hierarchical startup of plural voltage regulators. Sensing stable output power from the last of the voltage regulators triggers the configuration of one or more programmable devices. Circuitry and other resources of a hot-swappable circuit board are protected against electrical transient-related damage by virtue of the present teachings.

Abstract: An inspecting method for an object to be inspected is provided to bring probes of a probe card into electrical contact with a predetermined number of devices of target devices of the object at a time to inspect electrical characteristics of the target devices by moving a mounting table for mounting thereon the object under the control of a control unit. Upon completion of the inspection of the target devices, if inspection errors have occurred in specific devices of the target devices in a regular pattern, the target devices are re-examined, and when the re-examination is carried out, a contact position between the probe card and the object is displaced from a contact position in a previous inspection by a distance of at least one device to inspect electrical characteristics of the number of devices of the target devices at a time.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: A device includes a conductive via to provide an electrical path through a substrate. The device further includes a conductive element. The device further includes a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element. The conductive path enables testing of continuity of at least a portion of the conductive via. The fuse is configured to be disabled after the testing of the continuity of the conductive via.

Abstract: Devices and methods for enhancing electrical safety are provided herein. Devices testing the safety of light fixtures are provided. Also provided are a variety of testing tools for improving electrical safety. The devices are generally capable of wirelessly communicating with a computer, particularly a hand-held device such as a smart-phone or tablet. Methods for using the devices are also provided.

Abstract: A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.

Abstract: A sort probe gripper includes a body, a jaw mount inserted into the body, a plurality of grippers mounted in the jaw mount and an actuator sleeve slidable along the body to engage the plurality of grippers.

Abstract: An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.

Abstract: An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.

Abstract: Circuit boards are provided that include a functional portion and at least one removable test point portion. The removable test point portion may include test points which are accessed to verify whether the functional portion is operating properly or whether installed electronic components are electrically coupled to the board. If multiple boards are manufactured together on a single panel (in which the individual boards are broken off), the test points can be placed on bridges (e.g., removable portions) that connect the individual boards together during manufacturing and testing. Configurable test boards are also provided that can be adjusted to accommodate circuit boards of different size and electrical testing requirements. Methods and systems for testing these circuit boards are also provided.

Abstract: An electronic device testing apparatus for conveying electronic devices to be tested to sockets of a contact portion and bringing the electronic devices to be tested electrically contact with the sockets to conduct a test of electric characteristics of the electronic devices to be tested, comprising an image pickup portion that takes an image of the sockets; a memory portion that stores reference image data of the sockets in a state of not being attached with any electronic devices to be tested obtained by taking images by the image pickup portion; and a mislay determination portion that obtains check image data of the sockets from the image pickup portion, reads the reference image data from the memory portion, compares the check image data with the reference image data and determines whether any of the electronic devices to be tested remain on the sockets.

Abstract: Electronic circuits and methods are provided for use in hot-swappable circuit board applications. Circuitry detects an electrical ground connection and signals operation of a hot-swap controller. Detection of stable operating power causes a hierarchical startup of plural voltage regulators. Sensing stable output power from the last of the voltage regulators triggers the configuration of one or more programmable devices. Circuitry and other resources of a hot-swappable circuit board are protected against electrical transient-related damage by virtue of the present teachings.

Abstract: An apparatus for quickly determining a fault in an electric power system includes a current transformer, a current determination unit and a fault determination unit. The current transformer detects current supplied to the electric power system and outputs a current detection voltage. The current determination unit respectively compares the current detection voltage, the first-order differential voltage of the current detection voltage and the second-order differential voltage of the current detection voltage with predetermined first, second and third reference voltages. The fault determination unit determines whether a fault occurs based on the compared result of the current determination unit and generates a trip signal when it is determined that the fault has occurred.

Abstract: Disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group, a plurality of signal lines connected to the primary TSV group, a redundant TSV group and connection circuitry responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group.

Abstract: A noise-reduction method for processing a port is applied to a test target for testing or being burned in with software. At least one zero-Ohm resistor is provided with a first end thereof electrically connected to a device under test (DUT) of the test target and a second end thereof connected to a test port. Moreover, at least one grounding zero-Ohm resistor is provided with one end connected to ground and the other end is a floating end. After the test target is finished debugging or burned in with software, the connection of the first end and the DUT is disabled, and the second end is connected to ground through the floating end to reduce noise generation and improve a flexibility in circuit layout.

Abstract: A device and method for configuring a semiconductor circuit having at least two identical or similar functional units, the faulty unit being identified and deactivated if an error occurs in at least one of the identical or similar functional units.