Abstract: A pulsed high frequency monitor of the present invention monitors the power level of a pulsed high frequency on the basis of a transition pattern in which the power level changes in time series instead of monitoring the power level by comparing the power level of the pulsed high frequency with a threshold value. The pulsed high frequency monitor comprises: a DC circuit that converts the pulsed high frequency into DC and outputs the power level; a power level change detection circuit that detects a level change of the power level; and a transition pattern determination circuit that determines a time-series transition pattern of the power level on the basis of the level change detected by the power level change detection circuit.

Abstract: Devices, systems, and methods for determining gas characteristics to monitor transformer operation include extracting gas from transformer fluid for analysis.

Abstract: End element for the stator of an electric motor of a hermetically sealed refrigerant compressor including at least one isolating element, having a ring-like core, to cover an axial end portion of the stator and to isolate a stator core and stator windings. The end element includes several spring holders extending radially outside the isolating element, each spring holder being adapted to hold a spring for supporting the electric motor in a housing of the hermetically sealed refrigerant compressor. The spring holders are oriented parallel to the axis of the isolating element and an insertion part of each spring holder extends in a first axial direction beyond the neighboring area of the isolating element. The spring holders and the isolating element are integral parts of the end element. The spring holders are tiltable so that an extended part of a spring holder tilts radially inwards.

Abstract: The intelligent accompaniment generating system includes an input module, an analysis module, a generation module and a musical equipment. The input module is configured to receive a musical pattern signal derived from a raw signal. The analysis module is configured to analyze the musical pattern signal to extract a set of audio features, wherein the input module is configured to transmit the musical pattern signal to the analysis module. The generation module is configured to obtain a playing assistance information having an accompaniment pattern from the analysis module, wherein the accompaniment pattern has at least two parts having different onsets therebetween, and each onsets of the at least two parts is generated by an algorithm according to the set of audio features. The musical equipment includes a digital amplifier configured to output an accompaniment signal according to the accompaniment pattern.

Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.

Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.

Abstract: A linear compressor includes a frame including a frame body, a frame head that extends from a front end of the frame body, a flange groove defined in the frame head, and a body hole that passes through the frame body; a cylinder including a cylinder body inserted into the body hole, a cylinder flange, and a cylinder head provided on a front end of the cylinder flange; and a lock ring press-fitted to be coupled to the flange groove and provided in a space defined between the cylinder head and an inner circumferential surface of the flange groove.

Abstract: A method for calibrating a serial interconnection system having a first node, a second node, calibration nodes that are electrically connected in series by the serial interconnection system, and connection nodes corresponding to the serially connected calibration nodes, the connection nodes electrically connected in series by the serial interconnection system, the calibration method involving: for each of the calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, measuring the phase difference of signals appearing at the first and second nodes; from the measured phase differences for the calibration nodes, computing phase corrections for each of the calibration nodes; and applying the phase corrections computed for each of the calibration nodes to the corresponding connection nodes.

Abstract: There are provided an apparatus and a method for detecting a frequency, the apparatus including a signal converting unit removing a high frequency component from an input signal and then converting the input signal into a digital signal, an edge detecting unit detecting an edge of the digital to thereby generate an edge detection signal having a predetermined magnitude, and a frequency estimating unit generating a pulse signal based on the edge detection signal and averaging the pulse signal at a predetermined interval to thereby estimate a frequency of the input signal.

Abstract: This load connection state detection circuit includes a PNP type transistor whose emitter is connected to a power source terminal, a NPN type transistor where the emitter thereof is connected to the power source terminal, the collector thereof is connected to the base of the PNP type transistor, and the base thereof is connected to the collector of the PNP type transistor, and a diode inserted between the collector of the PNP type transistor and an external antenna load, wherein the diode is configured to perform temperature compensation for the base voltage of the NPN type transistor and prevent currents from flowing from the external antenna load to the PNP type transistor and the NPN type transistor.

Abstract: A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Abstract: There are provided an apparatus and a method for detecting a frequency, the apparatus including a signal converting unit removing a high frequency component from an input signal and then converting the input signal into a digital signal, an edge detecting unit detecting an edge of the digital to thereby generate an edge detection signal having a predetermined magnitude, and a frequency estimating unit generating a pulse signal based on the edge detection signal and averaging the pulse signal at a predetermined interval to thereby estimate a frequency of the input signal.

Abstract: A method is provided for measuring and modulating in real time the electrical consumption of electrical appliances. The method includes measuring in real time the current consumed by each of the electrical appliances on each electrical line portion on which each electrical appliance is situated and extracting the frequency and the voltage of the electrical signal on each electrical line portion. The difference in frequency are calculated and an alert signal is generated associated with an electrical line portion when the difference in frequency on this electrical line portion is greater than a predetermined frequency threshold value (fthreshold) and/or the difference in voltage on this electrical line portion is greater than a predetermined voltage threshold value (Vthreshold).

Abstract: Power saving for hot plug detect (HPD) is disclosed. In a particular embodiment, a method includes detecting, at a source device that is connectable to a sink device, a connection of the source device to the sink device via a connector. The source device includes a DC voltage source and the connection is detected without consuming power from the DC voltage source.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: A resume device is provided. The device detects voltage variation in standby mode. When a big voltage variation is detected, a resume process is run and a sound is played. Volume of the sound is adjustable and power is maintained within a proper range. Thus, power consumption is saved, efficiency is improved and resume process is enhanced.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: An integrated circuit for controlling a DC motor is disclosed. The integrated circuit includes at least one digital position and speed circuit (DPS) for providing measurements of speed, position, and direction of the motor, the DPS being in signal communication with the motor for receiving a pair of signals having a quadrature relationship; and at least one programmable gain amplifier (PGA) electrically coupled to the motor, the PGA being configured to receive a feedback signal indicative of current flowing through the motor and to apply a second signal to the motor for adjusting the speed of the motor; and at least two analog-to-digital converters (A/D), one A/D being used to quantize the output of the PGA for an off-chip processor; and another A/D to provide motor reference position from an analog sensor, such as a potentiometer; and at least two digital-to-analog converters (D/A), one D/A used to set the motor voltage; and another D/A used to set the motor current limit.

Abstract: An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine responsive to said sequence of logic values to switch the electronic system between different modes of operation.

Abstract: The present invention provides a digital oscilloscope with glitch detection, including a synchronous random access memory (RAM), a digital signal processing unit, coupled to the synchronous RAM, and a master control unit coupled to the digital signal processing unit. The digital signal processing unit includes an analog-to-digital (A/D) converter to digitize an analog signal and a digital signal processor. The digital signal processor includes a dual-port RAM, a plurality of processing blocks to process the digitized analog signal data, detect glitches in the digitized analog signal data, store the processed signal data in the synchronous RAM, create display data from the stored signal data, and store the display data in the dual-port RAM, and a communications interface to transmit the stored display data.

Abstract: Disclosed herein is a method and apparatus used to the measure duty cycle of a clocking waveform utilizing minimal hardware and achieving high accuracy. This invention utilizes digital sampling of the signal to be measured at a rate that can be significantly lower then the clocking frequency of the signal to be measured. It accomplishes broad-band, multi-frequency use by using a time-varying frequency for the sampling clock to make sure that the sampling clock is asynchronous with the frequency of the clocking signal to be measured. The average ratio of the sampled ones (or zeros) as compared to the total number of samples is then computed to derive the measurement of duty cycle.

Abstract: A built-in self-test apparatus for a digital-to-analog converter uses a differentiation unit for differentiating a digital-to-analog (DA) signal to obtain the differences between pulses of the analog signal. Next, the analog signal is converted into a digital signal in the light of a threshold voltage by a Schmitt trigger unit. Then, the duty cycles of the digital signal are calculated by a duty cycle retriever, and transmitted into a signature analyzer to calculate the differential non-linearity for error analysis. For processing a high-speed DA signal, the circuit disposed before the differentiation unit may use a test pattern unit, a sample-and-hold circuit and a logic circuit to lower the speed of the DA signal.

Abstract: To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.

Abstract: A data receiver, which could be an optical transceiver, a modem, a router hub, is capable of detecting the transmission rate of incoming data. The data is converted to electrical waves appropriate for passive or active bandpass filtering. The frequencies at which the waves are filtered are determined from a plurality of known possible transmission rates and are chosen as having the most detectable difference in the power spectra. By implementing a filter at the corresponding frequency(ies), data having that (those) frequency(ies) will be transmitted. A signal detector then can receive a signal transmitted through the filter and determine the corresponding data rate. It is further contemplated that the multiple frequencies can be filtered by using stages of filters and signal detectors for different frequencies or by filters and detectors capable of multiple frequency operation.

Abstract: A processor that utilizes the presence of harmonic components in a noisy signal environment to enhance the desired frequency spectrum of the signal. Received signal and noise are filtered to separate the harmonic components of the signal. These harmonic components are then combined in a prescribed manner to form a multiplicity of combined signals with varying harmonic content. The combined signals are then further processed to establish a signal detection.

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Abstract: A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

Abstract: A time measuring device includes: an input signal detecting unit for detecting three or more edges in an input signal and to output three or more detection signals in parallel, the three or more detection signals changing based on the three or more edges, respectively; a converting unit for converting phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit for counting, from change timings of at least two of the detection signals, number of the clock edges between the clock edges from which at least two detection signals are respectively delayed by the phase differences corresponding to at least two detection signals; an operating unit for calculating a time interval between edges of the three or more edges based on the analog voltage values and the number of clock edges.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: A digital frequency detector (10) and method for digitally detecting arbitrarily small phase changes between a signal waveform and a reference waveform. Both the reference waveform and the signal waveform are sampled at a rate related to the clock frequency fc, and separately fed into two arrays of simple frequency detectors (12, 14). Each simple frequency detector in each array has a different starting phase with respect to the reference waveform and the signal waveform respectively. Phase slips between the reference waveform and the sampling frequency and phase slips between the signal waveform and the sampling frequency are measured by the detector arrays (12, 14). These phase slips, called “slip events”, are combined in circuit (16) which produces an output indicative of phase slips between the reference waveform and the signal waveform. Using this phase slip information, the instantaneous frequency difference between the signal and reference waveforms can be determined.

Abstract: A circuit switching device or circuit breaker with integrated self-test enhancements is disclosed having separable contacts operable under processor control to control power to a circuit responsive to at least one of a plurality of fault conditions and operable according to a method for testing, including the steps of: controlling the switching device during a sampling cycle, to input one or more operating parameters sensed in the circuit to an A/D converter for measurement wherein the operating parameters enable detection of the fault conditions; determining whether to read a select one of the operating parameters from an output of the A/D converter into a first memory; and reading pre-determined parameter values from a second memory into the first memory during the sampling cycle instead of the operating parameters read from the A/D converter if a self-test has been invoked during the sampling cycle.

Abstract: Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.

Abstract: A spectrum analyzer is provided with a continuous period measurement function which continuously measures time periods of each and every cycle of an IF signal to analyze changes in frequency and time period of an input signal in a time domain. The frequency spectrum analyzer having a sweep local oscillator includes a continuous period measurement block for continuously measuring each time period of an IF signal produced by mixing the input signal and the local oscillator signal, and a processor and display for processing the data representing the continuous time period produced by the continuous period measurement block to analyze the input signal in the time domain.