Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: A catheter flexible printed wiring board which includes: a long flexible insulating base member having a tip end portion and a base end portion; and a conductive pattern formed on the flexible insulating base member and extending from the base end portion to the tip end portion, wherein the conductive pattern at the base end portion is wider than the conductive pattern at the tip end portion and thicker than the conductive pattern at the tip end portion.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A method of forming a current measurement device includes providing a glass substrate having first and second substantially planar surfaces that are opposite one another, forming a plurality of through-vias in the glass substrate that each extend between the first and second substantially planar surfaces, and forming conductive tracks on the glass substrate that connect adjacent ones of the through-vias together. Forming the plurality of through-vias includes applying radiation to the glass substrate, and the conductive tracks and the through-vias collectively form a coil structure in the glass substrate.

Abstract: Proposed is a multilayer wiring substrate having excellent joining strength, a method of manufacturing the multilayer wiring substrate, and a probe card having the multilayer wiring substrate.

Abstract: A semiconductor device includes: a first resistance chain including first upper resistance segments, first resistance via plugs, and first lower resistance segments; a second resistance chain including second upper resistance segments, second resistance via plugs, and second lower resistance segments; and a third resistance chain including third upper resistance segments, third resistance via plugs, and third lower resistance segments, wherein the first upper resistance segments have a first upper effective resistance distance, and the second upper resistance segments have a second upper effective resistance distance, and the third upper resistance segments have a third upper effective resistance distance, and the first upper effective resistance distance is equal to the third upper effective resistance distance, and the second upper effective resistance distance is an integer multiple of the first upper effective resistance distance.

Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.

Abstract: An inspection apparatus and a method of inspecting a semiconductor device are disclosed. The inspection apparatus includes a stage on which a semiconductor device is positioned, a first light source irradiating a high-frequency light onto an inspection area of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device, a beam scanner arranged over the semiconductor device and irradiating a charged particle beam onto the inspection area of the semiconductor device to generate secondary electrons, and a defect detector generating a detection image corresponding to the inspection area and detecting, based on a voltage contrast between a reference image and a plurality of detection images, a defect image indicating a defect in the semiconductor device from among the plurality of detection images.

Abstract: An apparatus includes an input probe configured to be placed on a first cluster of u-bumps disposed on a semiconductor die, output probes configured to be respectively placed on multiple clusters of u-bumps disposed on the semiconductor die, the multiple clusters being separately connected to the first cluster. The apparatus further includes a space transformer and printed circuit board (PCB) portion including a current source configured to supply a current to the input probe placed on the first cluster, resistors having a same resistance and being connected to ground, and tester channels at which voltages are respectively measured, the tester channels being respectively connected to ends of the output probes respectively placed on the multiple clusters and being respectively connected to the resistors. The apparatus further includes a processor configured to determine whether the input probe is properly aligned with the first cluster, based on the measured voltages.

Abstract: The disclosure provides a system that may: provide multiple first portions of a laser beam to an objective lens of an optical system; provide the multiple first portions of the laser beam to respective multiple locations of a test surface; receive multiple second portions of the laser beam from the test surface; determine multiple intensities respectively associated with the multiple second portions of the laser beam; transform the multiple intensities into data that represents multiple measurement values of the multiple intensities; determine, from the data, if an intensity value of the multiple intensities is below a threshold intensity value; if the intensity is below the threshold intensity value, provide information that indicates an issue associated with the objective lens; and if the intensity is not below the threshold intensity value, provide information that indicates there is no issue associated with the objective lens.

Abstract: The disclosure relates to technology for determining stress on integrated circuits. These include using ring oscillators formed on the integrated circuit, where one ring oscillator has its frequency dependent on the current flowing through its stages being limited by its NMOS devices and another ring oscillator has its frequency dependent on the current flowing through its stages being limited by its PMOS devices. This allows the stress on the integrated circuit to be determined in different directions along the integrated circuit. A temperature sensor can be used to compensate for temperature dependence on the frequencies of the ring oscillators.

Abstract: The present invention provides a probing system, which utilizes a suction nozzle to suck a wafer in probing. A relative distance between the suction nozzle and the probes can be adjusted according the conditions of the probing system, so the system extends the usage life.

Abstract: A high-speed circuit assembly includes a high-speed circuit including at least one waveguide/transmission line, and a radiation absorbing material disposed in contact with or in close proximity with the waveguide/transmission line.

Abstract: A probe assembly, adapted to test high-speed signal transmission lines of printed circuit boards, includes two pogo pins for providing high-frequency differential test signals, and both sides of the pogo pin include no metal layer (grounding layer). Experiments have found that when the two pogo pins test a to-be-tested object, the test signal will be coupled to the metal layers on both sides of the pogo pins to generate a radiation resonance, resulting in a loss of the test signal on a specific frequency band, and further reducing the effective bandwidth of the probe assembly. The metal layers on both sides of the pogo pins of the probe assembly are reduced, so that the foregoing radiation resonance phenomenon can be avoided.

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT.

Abstract: A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure.

Abstract: A micro camera is placed in an appropriate image capturing position therefor on the basis of a center-to-center distance depending on a rotational angle of a holding table. Even in the case where the center C0 of a holding surface and the center C1 of a wafer are displaced out of alignment with each other, allowing a position in X-axis directions of an outer circumference of the wafer to vary as the holding table rotates, a control unit can make an image capturing range of the micro camera follow the varying position of the outer circumference of the wafer. Therefore, the image capturing range of the micro camera can be determined with ease. Both a surface of the wafer and the outer circumference of the wafer can be inspected simply when two cameras are moved along the X-axis directions by a single X-axis moving mechanism.

Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.

Abstract: An inspection system is provided with a prober and a tester. The tester includes a plurality of tester module boards on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit which displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester; and a tester control unit which includes a wafer map drawing application for drawing the wafer map displayed on the display unit. The wafer map drawing application causes the inspection results and/or the self-diagnosis results to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively linked to correspond to the plurality of LSIs mounted on the plurality of tester module boards.

Abstract: A crack detection system and an apparatus equipped with a crack detection circuit, including a main body, and a detection control circuit and a detection coil disposed on the main body. The main body includes a top surface, a bottom surface, and a side surface coupled between the top surface and the bottom surface. The detection coil is distributed on an edge of the main body and disposed surrounding the side surface. Two ends of the detection coil are electrically coupled to the detection control circuit to form a closed-loop detection circuit. The detection circuit is configured to detect a crack in an edge region of the main body. The detection coil includes a plurality of detection sections sequentially coupled from head-to-tail, and adjacent detection sections are not collinear.

Abstract: A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure.

Abstract: A drive unit of a stage device includes a boxy body having a rectangular shape in a plan view, a base, a pair of X-axis linear motors, and a pair of Y-axis linear motors. An X-axis stator is disposed on each of two mutually opposing X-axis-direction side walls of the boxy body, wherein magnetic attractions that draw respective X-axis rotors toward the X-axis stator side (Y-axis direction) cancel out each other between the pair of X-axis linear motors. A Y-axis stator is disposed on the inside of each of two mutually opposing Y-axis wall members, wherein magnetic attractions that draw respective Y-axis rotors toward the Y-axis stator side (X-axis direction) cancel out each other between the pair of Y-axis linear motors.

Abstract: A crack detection system and an apparatus equipped with a crack detection circuit, including a main body, and a detection control circuit and a detection coil disposed on the main body. The main body includes a top surface, a bottom surface, and a side surface coupled between the top surface and the bottom surface. The detection coil is distributed on an edge of the main body and disposed surrounding the side surface. Two ends of the detection coil are electrically coupled to the detection control circuit to form a closed-loop detection circuit. The detection circuit is configured to detect a crack in an edge region of the main body. The detection coil includes a plurality of detection sections sequentially coupled from head-to-tail, and adjacent detection sections are not collinear.

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.

Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor structure including a cap layer and a channel layer forming a heterojunction, such that a two dimensional electron gas is formed at the interface of cap layer and the channel layer. The HEMT also includes a set of electrodes including a source electrode, a drain electrode, and a gate electrode deposited on the cap layer. The gate electrode is arranged between the source and the drain electrode along the length of the HEMT. The thickness of the cap layer at least under the gate electrode is varying along the width of the HEMT.

Abstract: Systems and methods for determining wafer bias are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model.

Abstract: Systems and methods of monitoring a discharge in a plasma process are disclosed. The methods include supplying the plasma process with a periodic power supply signal, determining a first signal waveform in a first time interval within a first period of the power supply signal, determining a second signal waveform in a second time interval within a second period of the power supply signal, the second time interval being at a position within the second period corresponding to a position of the first time interval within the first period, comparing the second signal waveform with a reference signal waveform to obtain a first comparison result, determining that the first comparison result corresponds to a given first comparison result, and in response, time-shifting one of the second signal waveform and the reference signal waveform, and comparing the time-shifted signal waveform with the non-time-shifted signal waveform to obtain a second comparison result.

Abstract: A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

Abstract: Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.

Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Abstract: Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

Abstract: A read circuit of an electrical signal produced by a POSFET device comprising a transconductance amplifier connected at an inverting input thereof to the output of the POSFET device; and at least one neuron connected at the output to the transconductance amplifier. The transconductance amplifier is adapted to: receive a signal coming from the POSFET device representative of a force or pressure exerted on the POSFET device, and produce at the output at least one current signal representative of the force or the pressure. The at least one neuron is adapted to receive said at least one current signal and to produce at least one output signal, said at least one output signal being a pulse train having a frequency proportional to said at least one current signal produced by the transconductance amplifier.

Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.

Abstract: An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe board spaced from the wiring base plate with a first surface thereof opposed to the wiring base plate and having a wiring path corresponding to the wiring path and probes provided on a second surface of the probe board to be connected to the wiring path and enabling to respectively contact connection pads of a semiconductor wafer on the chuck top, and an electric connector connecting the wiring base plate to the probe board by low heat conduction supporting members and decreasing heat conduction therebetween and electrically connecting the wiring paths.

Abstract: An adapter as disclosed herein includes at least one transmission path providing an electrical connection between the probing end and the head connection end. The adapter includes a flexible tab-board adapter associated with the probing end of the transmission path, the flexible tab-board adapter for contacting at least one signal testing point. The adapter may further include at least one compensating network positioned substantially near the probing end, the at least one compensating network configured to compensate for parasitics of the adapter.

Abstract: A test key structure includes a plurality of transistors formed on a scribe line of a wafer and arranged in a 2*N array having 2 columns and N rows. The transistors arranged in the 2*N array respectively includes a gate, a source, a drain, and a body. All of the sources of the transistors arranged in the 2*N array are electrically connected to each other.

Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

Abstract: A method for accurately determining the sheet resistance and leakage current density of a shallow implant in a semiconductor substrate surface includes making one or more four-point resistance measurements with an induced current below 100 ?A on the semiconductor surface with a plurality of electrode spacing sets, at least one set defining an electrode separation distance less than 100 ?m. The sheet resistance and implant leakage are determined through fitting the measured data to theoretical data to within a predetermined error margin.

Abstract: The wafer inspection interface 18 includes a probe card 20 having a multiple number of probes 25; a fixing ring 21 configured to hold the probe card 20; a chuck top 23 disposed to face the probe card 20 with a wafer W therebetween; an outer seal ring 24 provided to hermetically seal an outer space 27 surrounded by the fixing ring 21, the probe card 20 and the chuck top 23; an outer depressurization path 29 through which the outer space 27 is depressurized; an inner seal ring 26 provided to hermetically seal an inner space 28 surrounded by the probe card 20 and the wafer W; and an inner depressurization path 30 through which the inner space 28 is depressurized. Further, the inner space 28 may be surrounded by the outer space 27, and the wafer W is disposed within the inner space 28.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A semiconductor device includes a test control unit suitable for activating an on-die termination signal in response to a control signal activated in a test mode, and a data mask pad suitable for pull-down driving a data mask signal when the on-die termination signal is activated.

Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.