Abstract: Provided is a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current flow path therethrough. The switching transistor becomes conductive in response to the control signal having a first value. The current flow path through the switching transistor provides a current flow line between two nodes. In a non-conductive state, a voltage drop stress is across the switching transistor. The circuit comprises a sense transistor that is coupled to and a scaled replica of the switching transistor. The sense transistor has a sense current therethrough. The sense current is indicative of the current of the switching transistor. The circuit includes coupling circuitry configured to apply the voltage drop stress across the sense transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated across both the switching transistor and the sense transistor.

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Abstract: In an ignition apparatus, a deterioration determination circuit performs a deterioration determination task of (i) monitoring an absolute increase in a temperature parameter during a predetermined deterioration detection period that has been started since an energization command signal being inputted to a control circuit, and (ii) performing a comparison between the absolute increase in the temperature parameter and a predetermined deterioration detection threshold to thereby determine whether a level of deterioration of a switching circuit is within an acceptable level.

Abstract: A power switch circuit with current sensing is disclosed. The power switch circuit is coupled between an input voltage and an output terminal. The power switch circuit includes a power switch, a first sensing switch, an adjusting circuit and a second sensing switch. The power switch is coupled to the input voltage. The first sensing switch is coupled in series between the power switch and the output terminal. There is a first node between the first sensing switch and the power switch. The adjusting circuit is coupled to the first node. The second sensing switch is coupled between the adjusting circuit and the output terminal. A control terminal of the power switch is coupled to a first control voltage. Control terminals of the first sensing switch and the second sensing switch are coupled to a second control voltage. The second control voltage is different from the first control voltage.

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).

Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Abstract: Provided is a testing apparatus for testing a semiconductor device including a first main terminal to which a first power source voltage is applied and a second main terminal to which a second power source voltage is applied, comprising: a condition setting unit for setting a changing speed of a terminal voltage of the first main terminal at turn-off of the device; an operation controlling unit for turning off the device under a condition set by the condition setting unit; and a determining unit for screening the device based on an operation result of the device, wherein: a time waveform of the terminal voltage at turn-off of the device includes a maximum changing point where a changing speed becomes maximum; and the condition setting unit sets the changing speed at a first set voltage higher than a voltage at the maximum changing point, to a predetermined value.

Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

Abstract: An electrical combination, a motorized device system, a motor assembly, a battery pack, and operating methods. The combination may include an electrical device including a device housing, a load supported by the device housing, the load being operable to output at least about 1800 watts (W), and a device terminal electrically connected to the load; a battery pack including a pack housing, battery cells supported by the pack housing, the battery cells being electrically connected and having a nominal voltage of up to about 20 volts, and a pack terminal electrically connectable to the device terminal to transfer current between the battery pack and the electrical device; and a controller operable to control the transfer of current.

Abstract: A test system, a method for manufacturing an electronic device, and a method for testing a wafer or electronic device that includes coupling a transistor in a series circuit with a capacitor and a resistor, coupling a voltage source to the capacitor to charge the capacitor to a non-zero DC voltage while the transistor is turned off, disconnecting the voltage source from the capacitor while the transistor is turned off, turning the transistor on while the voltage source is disconnected from the capacitor, measuring a voltage signal across the resistor while the transistor is turned on, and determining a test result indicating whether the transistor has an acceptable dynamic on-state resistance according to the voltage signal across the resistor.

Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.

Abstract: A method for testing and analyzing a display panel, comprising: providing a display panel including a circuitry and a pixel connected to the circuitry, wherein the pixel includes a capacitor, a transistor and an electrode electrically connected to the capacitor and the transistor; measuring a first parameter of the display panel; disabling the pixel; measuring a second parameter of the display panel; and deriving a third parameter of the pixel by subtracting the second parameter from the first parameter.

Abstract: Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.

Abstract: Systems and methods for testing radio frequency FET switches at high RF voltages. Embodiments utilize an impedance transformer, or resonator, to step up the available voltage from an RF signal generator and amplifier to a device under test (DUT). The resonator reduces the RF power required to test at higher voltages, resulting in lower cost and other benefits. When a DUT begins to exhibit excessive non-linear distortion, resonance is lost, applied RF test signal power is reflected back as a reflected signal, and current to the DUT is starved by the resonator, protecting the DUT from destructive power levels. Measuring the amplitude of the reflected signal at the harmonic frequencies of the RF test signal allows detection of a harmonic knee point for selected reflected signal harmonics, and consequently allows determination of the power level of the RF test signal at which excessive non-linear distortion occurs.

Abstract: Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

Abstract: A probe card includes a printed circuit board (PCB), a connection substrate electrically connected with the PCB, a probe head, and a signal path switching module disposed on a lateral periphery surface or a bottom surface of the connection substrate, electrically connected with probe needles of the probe head and the connection substrate and including first and second circuit lines with first and second inductors respectively, and a capacitor electrically connected between the first and second circuit lines. A test signal from a tester is transmitted between the tester and a device under test (DUT) via the PCB, the connection substrate, the first and second circuit lines and the probe needles. A loopback test signal from the DUT is transmitted back to the DUT via the probe needles, parts of the first and second circuit lines and the capacitor.

Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Abstract: A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node.

Abstract: A detection method and a detection device of a display pane are provided. The detection method includes: detecting an actual value of an electric signal at a first electrode of a driving transistor in each of pixel units when the display panel reaches target brightness, the electric signal including a current signal and/or a voltage signal; and determining according to the actual value of the electrical signal corresponding to each of the pixel units, whether each of the pixel units is defective. The present disclosure may help an operator determine if each of the pixel units is defective quickly.

Abstract: A measurement apparatus (1) comprising a high frequency measurement unit (2) adapted to measure high frequency parameters (HFP) of a device under test (DUT) connected to ports of said measurement apparatus (1) and a multimeter unit (3) adapted to measure DC characteristics parameters (DCP) of said device under test (DUT) connected via control signal lines (CL) to a control bus interface (6) of said measurement apparatus (1).

Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

Abstract: A test circuit, a test method, an array substrate and a manufacturing method thereof are provided. The test circuit includes a plurality of to-be-tested units and plurality of test electrodes connected to the to-be-tested units. The plurality of to-be-tested units are arranged in a matrix. At least one of the test electrodes is multiplexed by the plurality of to-be-tested units in a row direction and at least one of the test electrodes is multiplexed by the plurality of to-be-tested units in a column direction.

Abstract: A pulse laser test system including a conditioning pulse circuit, a probe pulse circuit, a pulse laser, a trigger mode controller, and a laser pulse modulator. The conditioning pulse circuit provides asynchronous conditioning trigger pulses at a selected rate. The probe pulse circuit provides a synchronized probe trigger pulse. The trigger mode controller selects the probe pulse circuit while the synchronized probe trigger pulse is provided causing the pulse laser to provide a synchronized probe laser pulse, and otherwise selects the output of the conditioning pulse circuit causing the pulse laser to provide asynchronous conditioning laser pulses. The laser pulse modulator has an optical input coupled to the laser output of the pulse laser, has a gating input receiving a gate signal from the trigger mode controller, and has an optical output that provides laser pulses passed from the pulse laser while the gate signal is asserted.

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

Abstract: Disclosed is a method for optimizing a wetting current, for a device for monitoring sensors with contact switches including a current source and at least two switch/resistor assemblies (CT1/R1, CT2/R2) in parallel, including the following steps: the current source (A) supplies the circuit with a nominal current; if a voltage (Vm) measured across the terminals of the switch/resistor assemblies is greater than a threshold voltage (Vs), the threshold voltage being lower than the supply voltage of the current source and than the saturation voltage of the analog-to-digital converter (CAN), then the current source is stopped and a unit for discharging the circuit are implemented; and the current source supplies the circuit again with a supply current (Iwet_c) equal to the nominal current reduced by a predetermined increment. These two last steps are repeated until the measured voltage is lower than the threshold voltage.

Abstract: A computer-implemented method capable of evaluating a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed is provided. The method may include receiving parameters relating to the transistor, receiving parameters relating to an interconnection, receiving parameters relating to the plasma-based process, assigning first potentials to terminals of the transistor, calculating second potentials at the terminals of the transistor, and determining a degradation state of the transistor according to the second potentials at the terminals of the transistor.

Abstract: A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Abstract: A threshold voltage measuring device may include a metal-oxide-semiconductor (MOS) transistor, a drain voltage clamping circuit configured to control a drain voltage of the MOS transistor wherein the drain voltage having a substantially constant level, and a constant current supply circuit configured to cause a drain-source current to flow through the MOS transistor wherein the drain-source current having a substantially constant magnitude.

Abstract: An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

Abstract: An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.

Abstract: Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process is essentially nullified.

Abstract: Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Abstract: A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port.

Abstract: A power amplifier (PA) system includes an amplifying transistor having a base, a collector, and an emitter. The PA system further includes a radio-frequency (RF) input configured to receive an RF input signal having an RF component and a DC bias component, a bias circuit coupled to the base of the amplifying transistor, and a bias tee circuit configured to receive the RF input signal and pass at least a portion of the DC component to the bias circuit and at least a portion of the RF component to the base of the amplifying transistor.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract: Bias tees, according to certain embodiments of the present invention, include switches in the AC signal path, the DC signal path, or both, to improve the capability of the bias tees to be used for high impedance AC measurement, low current DC measurement, or both. Optical control of the switches, as well as control of the switches using a DC bias present within the AC signal input to the bias tee, is described. Including a set of diodes into the DC signal path, rather than a switch, provides enhanced capability of the bias tee to be used for high impedance AC measurements.

Abstract: Electrical conductance measurement system including a one-dimensional semiconducting channel, with electrical conductance sensitive to electrostatic fluctuations, in a circuit for measuring channel electrical current. An electrically-conductive element is disposed at a location at which the element is capacitively coupled to the channel; a midpoint of the element aligned with about a midpoint of the channel, and connected to first and second electrically-conductive contact pads that are together in a circuit connected to apply a changing voltage across the element. The electrically-conductive contact pads are laterally spaced from the midpoint of the element by a distance of at least about three times a screening length of the element, given in SI units as (K?0/e2D(EF))1/2, where K is the static dielectric constant, ?0 is the permittivity of free space, e is electron charge, and D(EF) is the density of states at the Fermi energy for the element.

Abstract: Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an SRAM word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the ASV.

Abstract: A test system measures parameters of a device under test (DUT), including a transistor. The test system includes a first voltage source unit for supplying a gate voltage; a second voltage source unit for supplying one of a drain voltage or a source voltage, the second voltage source having a current measurement device for detecting one of a drain current or a source current flowing through the transistor, respectively; a feedback unit for outputting a feedback current, based on the one of the drain or source currents; and an error amplifier for outputting a feedback control signal, based on comparison of the feedback current and a target current value. The first voltage source unit adjusts the gate voltage based on the feedback control signal so that the one of the drain or source currents converges to match the target current value.

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract: According to example embodiments, a method for controlling a gate voltage applied to a gate electrode of a high electron mobility transistor (HEMT) may include measuring a voltage between a drain electrode and a source electrode of the HEMT, and adjusting a level of the gate voltage applied to the gate electrode of the HEMT according to the measured voltage. The level of the gate electrode may be adjusted if the voltage between the drain electrode and the source electrode is different than a set value.

Abstract: An electronic power circuit, electrical machine and a method for verifying the functionality of an electronic power circuit. The invention relates to an electronic power circuit, an electrical machine with the electronic power circuit and a method for verifying the functionality of the electronic power circuit. The electronic power circuit comprises a power unit with at least one power semi-conductor switch, which is equipped to generate a pulsed electrical voltage for an electrical consumer from an electrical voltage on the basis of an alternating powering on and off of the at least one power semiconductor switch, and control electronics equipped to control the power semiconductor switch for the alternating powering on and off.

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

Abstract: A mechanism is described for facilitating and employing a modular processing cell framework according to one embodiment. A method of embodiments may include accepting one or more semiconductor devices in one or more media at a modular processing cell framework (“framework”) including a plurality of test cells, moving the one or more semiconductor devices from the one or more media to one or more test cells for testing; and testing the one or more semiconductor devices.

Abstract: There is provided a physical property measuring method for a TFT liquid crystal panel, includes an impedance setting step of setting the impedance between the source and drain of a TFT of the TFT liquid crystal panel to be less than or equal to a predetermined value, a voltage application step of applying a voltage that cyclically varies to a liquid crystal layer of the TFT liquid crystal panel. And the method further includes a physical property measuring step of measuring a transient current flowing through the liquid crystal layer to which the voltage that cyclically varies is applied in the voltage application step to measure physical properties of the liquid crystal layer.