Abstract: A measuring instrument for detecting a source of passive intermodulation (PIM) includes a first signal source, a second source and a receiver. The first and second signal sources are each connected with separate transmit antenna to transmit a first and second signal, respectively. The first transmit antenna and the second transmit antenna are arranged in a fixed relationship relative to each other such that the first signal and the second signal are combinable to generate a PIM signal at a PIM. The receiver is connected with a receive antenna and arranged in a fixed relationship relative to the first transmit antenna and the second transmit antenna to receive the PIM signal reradiated from the PIM source. The receiver is configured to receive the PIM signal and indicate detection of the PIM source in response to receiving the PIM signal.

Abstract: A method of material analysis, including; placing an electrode in proximity to the material; applying a voltage signal to generate plasma, preferably Dielectric Barrier Discharge in Air, between the material and the electrode; moving the electrode relative to the surface; monitoring an electrical signal associated with the microdischarge; and detecting a change in a physical characteristic of the material through variation in the monitored signal.

Abstract: Methods and systems for reducing wafer shape and thickness measurement errors resulted from cavity shape changes are disclosed. Cavity calibration process is performed immediately before the wafer measurement. Calibrating the cavity characteristics every time the method is executed reduces wafer shape and thickness measurement errors resulted from cavity shape changes. Additionally or alternatively, a polynomial fitting process utilizing a polynomial of at least a second order is utilized for cavity tilt estimation. High order cavity shape information generated using high order polynomials takes into consideration cavity shape changes due to temperature variations, stress or the like, effectively increases accuracy of the wafer shape and thickness information computed.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: A signal test apparatus for a serial attached Small Computer System Interface (SAS) device includes an SAS female connector to be connected to the SAS device, an SAS male connector to be connected to a server, first and second pairs of subminiature version A (SMA) connectors, and first and second groups of switches. When the first pair of SMA connectors is connected to an oscillograph to test a pair of output signals from the SAS device, the second group of switches are turned on and the first group of switches are turned off to communicate the SAS device with the server. When the second pair of SMA connector is connected to the oscillograph to test another pair of output signals from the SAS device, the first group of switches are turned on and the second group of switches are turned off to communicate the SAS device with the server.

Abstract: A signal detection apparatus for a serial attached SCSI (SAS) device includes an SAS female connector to be connected to a SAS device, an SAS male connector to be connected to a system, and first to fourth pairs of subminiature version A (SMA) connectors. When the first pair of SMA connectors is connected to an oscillograph to detect a pair of output signals from the SAS device, the second and third pairs of SMA connectors connect the SAS device with the system. When the second pair of SMA connector is connected to the oscillograph to detect another pair of output signals from the SAS device, the first and fourth pairs of SMA connectors connect the SAS device with the system.

Abstract: A semiconductor apparatus (IPD) includes a set value storage unit that stores a set value determined based on an initial characteristic value of the IPD, and a detector that detects characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the set value stored in the set value storage unit. Further, a method of detecting characteristic degradation of a semiconductor apparatus (IPD) includes storing a set value determined based on an initial characteristic value of the IPD, and detecting characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the stored set value.

Abstract: A time dependent dielectric breakdown (TDDB) test structure of a semiconductor device includes: a first test cell having a first test pattern in which a dielectric layer is formed between two electrodes; a second test cell spaced apart from the first test cell and having a second test pattern in which a dielectric layer is formed between two electrodes; and a barrier region configured to prevent electrical interference from occurring between the first test cell and the second test cell during a TDDB test.

Abstract: A probe includes a wire and a bump, wherein the wire is formed on a substrate; and the bump is formed upon the wire. In addition, a probe block includes a plurality of probes disposed on a substrate, so that the probe block is composed of a plurality of wires and bumps. The wires are disposed on the substrate and each bump is disposed accurately upon an end of each wire. The bump and the wire of the probe in accordance with the present invention are formed jointlessly. A method of fabricating the probe is characterized in that a grayscale mask is utilized to form the wire on the substrate and form the bump upon the wire by using a single masking process.

Abstract: The present invention relates to a test equipment of direct current thyristor valve, and particularly relates to a fault current test equipment of direct current thyristor valve. This present invention equipment includes high voltage low current circuit and low voltage high current circuit, said test equipment includes fault current circuit, said fault current circuit includes resonant circuit, said high voltage low current circuit, low voltage high current circuit and fault current circuit are all connected with the thyristor sample Vt respectively. In his present invention, the thyristor sample is first heated through the high voltage circuit and low voltage high current circuit to reach the stable state. And then shut off the switch and carries out the test using the fault current which is produced by the fault current circuit. This prevents the power system from the short-circuit impact.

Abstract: Improved probing of closely spaced contact pads is provided by an array of vertical probes having all of the probe tips aligned along a single contact line, while the probe bases are arranged in an array having two or more rows parallel to the contact line. With this arrangement of probes, the probe base thickness can be made greater than the contact pad spacing along the contact line, thereby advantageously increasing the lateral stiffness of the probes. The probe tip thickness is less than the contact pad spacing, so probes suitable for practicing the invention have a wide base section and a narrow tip section.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: A method comprising applying a first voltage to a first transistor to create a defect in the first transistor, wherein (i) the first voltage is greater than a maximum operational voltage of the first transistor and (ii) the maximum operational voltage does not cause a defect in the first transistor when applied to the first transistor. The method further includes determining whether the first transistor has been programmed, including (i) measuring a first current through the first transistor, (ii) measuring a second current through a second transistor, and (iii) comparing the measured first current to the measured second current, wherein a difference between the measured first current and the measured second current indicates that the first transistor has been programmed.

Abstract: An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.

Abstract: The present invention relates to a method for evaluating the SOI wafer in a method for evaluating an SOI wafer in which a sheet resistance of a buried diffusion layer of an SOI wafer that has at least an SOI layer on an insulator layer and has a buried diffusion layer whose impurity concentration is higher than other region of the SOI layer in an interface area with the insulator layer of the SOI layer is evaluated, the method including the steps of measuring a sheet resistance of the whole SOI layer or the whole SOI wafer, and estimating the sheet resistance of the buried diffusion layer by assuming respective layers that compose the SOI wafer to be resistors connected in parallel and converting the measured result of the sheet resistance measurement. As a result of this, there is provided a method for evaluating the SOI wafer that can directly measure the SOI wafer itself to be the product to thereby evaluate the sheet resistance of the buried diffusion layer thereof, without fabricating a monitor wafer.

Abstract: A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.

Abstract: Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to outputs of the scan chains. The verification unit is configured to determine the validity of the outputs of the scan chains and to indicate a malfunction of the integrated circuit if the outputs are determined not to be valid.

Abstract: A method for monitoring device characteristics of semiconductor integrated circuits. The device characteristics includes censored data and uncensored data. The method includes determining a plurality of minimum breakdown voltages numbered from 1 through N, respectively, for a plurality of lots (e.g., wafer fabrication lots) numbered from 1 through N. Each of the plurality of minimum breakdown voltages is respectively indicative of the plurality of samples through order statistics. One or more of the plurality of samples includes one or more uncensored data points and one or more censored data points. The method includes processing the minimum breakdown voltages, respectively, for the plurality of lots. Each of the minimum breakdown voltages is processed for the respective plurality of lots and is indicative of a population characteristic breakdown voltage numbered from 1 through N for the respective lot numbered from 1 through N.