Abstract: Various design concepts, circuit implementations, and methods are provided for implementing temporal memory. For example, temporal memories may perform both read and write operations using time-encoded wavefronts. A temporal memory may include a group of tunable delay components that “store” time-encoding information. Using these delay components, the memory can perform a “read” operation by outputting wavefronts having the same or similar time-encoding as the stored wavefronts. Temporal memories may allow for more energy-cost-efficient operation and may serve as building blocks for more complex temporal computational circuits.

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

Abstract: The present disclosure discloses a Single-Event Transient (SET) pulse measuring circuit capable of eliminating impact thereof, and an integrated circuit chip. The SET pulse measuring circuit capable of eliminating impact thereof includes four parts: a SET pulse test chain, a latch circuit, a flip-flop test circuit, a latching self-trigger circuit. The integrated circuit chip is provided with a test chain module and two sets of SET pulse measuring circuits capable of eliminating impact thereof, and inputs of the two sets of SET pulse measuring circuits capable of eliminating impact thereof are the same and each are connected to an output terminal of the test chain module.

Abstract: This technology is directed to a rules based engine for managing network-based scanning of devices on a network to minimize disruptions to the network. One or more processors may identify an initial group of network devices from a set of network devices, the initial group of network devices being identified in accordance with a rule set, and initiate a scan of the initial group of network devices. The one or more processors may determine, in accordance with the rule set, an additional group of network devices from the set of network devices to be scanned and initiate a scan of the additional group of network devices. The steps may be repeated until all network devices in the set of network devices are scanned in accordance with the rule set.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for variable termination in a vehicle communication bus. To provide compatibility with multiple vehicles, a device may include a software selectable terminator resistor that can be programmatically enabled or disabled to add or remove resistance as needed. For example, the software selectable terminator resistor may be enabled when the device is added as an end node in a high-speed communication bus and operates as a terminator resistor. Alternatively, the software selectable terminator resistor may be disabled when the device is added as an intermediate node positioned between terminator resistors in the high-speed communication bus.

Abstract: An apparatus is provided that includes a control unit and a memory including computer program code. The apparatus is capable of applying a first signal having a first value and a second signal having a second value to an electronic component and receiving a first feedback signal. The apparatus is capable of determining a first parameter associated with the first feedback signal. The apparatus is capable of applying a third signal having a third value and the second signal to the electronic component and receiving a second feedback signal. The apparatus is capable of determining a second parameter associated with the second feedback signal. The apparatus is capable of applying a fourth signal having a fourth value and the second signal to the electronic component if the first parameter is different from the second parameter.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

Abstract: The present invention relates to a display device, a gate driving circuit, and a driving method thereof, and more specifically, to a display device, a gate driving circuit, and a driving method thereof capable of solving problems with insufficient charging time or image abnormalities by controlling supply timing of two gate signals, e.g., scan signals and sense signals.

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for variable termination in a vehicle communication bus. To provide compatibility with multiple vehicles, a device may include a software selectable terminator resistor that can be programmatically enabled or disabled to add or remove resistance as needed. For example, the software selectable terminator resistor may be enabled when the device is added as an end node in a high-speed communication bus and operates as a terminator resistor. Alternatively, the software selectable terminator resistor may be disabled when the device is added as an intermediate node positioned between terminator resistors in the high-speed communication bus.

Abstract: Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

Abstract: According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.

Abstract: A display driver (10) includes a power supply circuit (60) that generates at least one power supply voltage, a drive circuit (20) that drives an electro-optical panel (150) based on the at least one power supply voltage, and a control circuit (50) that controls the power supply circuit (60) based on a control signal, a first monitoring circuit (M1) that monitors the control signal on the control circuit (50) side, and a second monitoring circuit (M2) that monitors the control signal on the power supply circuit (60) side.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

Abstract: A microcomputer is connected to a logic circuit. The microcomputer includes a monitoring unit monitoring the state of the logic circuit, a storage unit storing a plurality of information processing items executed by the microcomputer, and a processing unit executing a process on the basis of the state of the logic circuit and at least one information processing item selected from the plurality of information processing items on the basis of a communication frame inputted to the microcomputer.

Abstract: A system comprises an electromagnetic pulse generation system that comprises a first pulse generation circuit, a second pulse generation circuit, and a mixing circuit. The electromagnetic pulse generation system is operable to output a first pulse generated by the first pulse generation circuit onto a first signal path, output a second pulse generated by the second pulse generation circuit onto the first signal path, generate a third pulse by mixing, via the mixing circuit, a fourth pulse generated by the first pulse generation circuit and a fifth pulse generated by the second pulse generation circuit, and output the third pulse on the first signal path.

Abstract: A provided impedance measuring semiconductor circuit can suppress the influence of sensors on the measurements of other sensors in the measurements of the sensors. According to an embodiment, an impedance measuring semiconductor circuit includes a first resistance element, an operational amplifier having a positive input terminal and an output terminal, the positive input terminal receiving a predetermined set voltage, the output terminal being coupled to one end of the first resistance element, a first output-side switch that electrically couples or decouples a first sensor and the other end of the first resistance element, a second output-side switch that electrically couples or decouples a second sensor and the other end of the first resistance element, a first input-side switch that electrically couples or decouples the first sensor and a negative input terminal, and a second input-side switch that electrically couples or decouples the second sensor and the negative input terminal.

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: A configurable processor comprises at least an array of configurable computing elements (CCE's). Each CCE comprises at least a three-dimensional (3-D) memory (3D-M) array; an arithmetic logic circuit (ALC); and, a plurality of inter-storage-processor (ISP) connections. Not penetrating through any semiconductor substrate, the ISP-connections are short, small and numerous.

Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: A level shifter device and an operation method thereof are provided. The level shifter device includes a buffer, a first level shifter and a dynamic voltage regulation circuit. The buffer includes an output terminal. The first level shifter has a first input terminal coupled to the output terminal of the buffer. The first level shifter has a reference voltage terminal coupled to an analog reference voltage. The dynamic voltage regulation circuit generates a dynamic voltage having a level varied according to a bounce of the analog reference voltage, and provides the dynamic voltage to at least one of the buffer as a power supply and the first level shifter as a bias voltage.

Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.

Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.

Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were in a predetermined state, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.

Abstract: To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.

Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were all positive, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.

Abstract: A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

Abstract: This disclosure is directed to processor state integrity protection using hash verification. A device may comprise processing circuitry and memory circuitry. The processing circuity may be triggered to enter a secure mode. Prior to entering the secure mode, the processing circuitry may determine a processor state of the processing circuitry and a hash of the processor state, and store them in secured memory within the memory circuitry. Prior to exiting the secure mode, the processing circuitry may compute an updated hash of the stored processor state and compare it to the previously stored hash. If the updated hash and stored hash are determined to be the same, then the processing circuitry may restore the processor state and normal operation resumes. If the updated hash and stored hash are determined to be different, then the stored processor state may be compromised and the processing circuitry may perform at least one protective action.

Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.

Abstract: Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.

Abstract: According to one embodiment, a data communication system includes: a data transmitting device that transmits a test pattern; and a data receiving device that receives the test pattern. The data receiving device receives the test pattern with every change in a threshold for determining whether received data is High or Low, compares the test pattern to an expected value for the respective changed thresholds, and selects the threshold based on the result of comparison between the test pattern and the expected value.

Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

Abstract: A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The configurable registers in each configuration group are connected in a looped one-way daisy chain. During its operation, each of the slave configuration controllers is configured to receive instructions from a user via a master configuration controller (MCC), performs read or write operations on the configurable registers of one of the configuration groups as designated by the instructions from the user.

Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.