Abstract: A buffer circuit includes a first PNP BJT having a first base, a first collector and a first emitter. A first diode has a first cathode and a first anode. The first cathode couples to the first PNP BJT. A second diode has a second cathode and a second anode. The second anode couple to first base, and the second cathode couples to the first emitter. A voltage level shifter circuit coupled to the first anode. The voltage level shifter has a voltage level shifter output. A pre-driver circuit has a pre-driver input coupled to the voltage level shifter output. A second transistor has a second base, a second collector and a second emitter. The second base couples to the output of the pre-driver output. The second collector couples to a negative supply voltage node. The second emitter couples to an output node of the buffer circuit.

Abstract: A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.

Abstract: A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain.

Abstract: A gate drive circuit creates a bipolar voltage to a gate of an IGB power transistor, and compensates for Miller currents of the IGB power transistor. The compensating is performed by a switching element connected in series with a capacitor between the gate (X4) and a supply voltage.

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract: Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Abstract: A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: An electric current switch circuit in accordance with the present invention is arranged so that an output of an IIL logic circuit is connected with the base of the first transistor of NPN type that switches ON or OFF the electric current. The first constant current source and the second transistor cause the first transistor to switch ON during a period when the output of the IIL logic circuit is in an OFF state, to switch OFF during a period when the output of the IIL logic circuit is in an ON state. Thus, only a voltage of 0.9V to 1.1V (the sum of a drop voltage across the first resistor and the base-emitter voltage) is applied to the base of the first transistor. Accordingly, a voltage less than the withstand voltage of the IIL logic circuit is applied to the base of the first transistor.

Abstract: A TTL gate (26) with a Darlington output (14,14A,16) includes three circuits (28,30,32) to decrease the gate switching time during an output transition from a high to a low logic state and from a high impedance state to a low logic state. Each speedup circuit drives the gate input transistor (12) for a different length of time, ensuring that the lower output transistor (16) turns on rapidly and remains on until the output transition is complete. The circuits ensure, however, that the additional drive current (82) is time limited to avoid excessive power consumption.