Abstract: Technologies relating to using a slew rate controller to reduce disturbance in a crossbar array circuit are disclosed. An example crossbar array circuit includes: one or more bit lines; one or more word lines; one or more 1T1R cells connected between the bit lines and the word lines; one or more ADCs connected to the one or more bit lines; one or more DACs connected to the one or more word lines; one or more access controls connected to the one or more 1T1R cells and configured to select a 1T1R cell in the one or more 1T1R cells and to program the selected 1T1R cell; and a slew rate controller connected to the DACs, wherein the slew rate controller is configured to receive an input signal. The slew rate controller may be configured to transform a step function input signal into a slew rate input signal.

Abstract: An apparatus may include an electric power converter and pre-charge circuitry. The electric power converter may include a first circuit, a second circuit and an energy transfer device. The first circuit may be connected to a power supply. The second circuit may be connected to a load. The energy transfer device may have a first side connected to the first circuit and a second side connected to the second circuit. The pre-charge circuitry may be connected to a capacitor of the first circuit. The capacitor may be connected to the first side of the energy transfer device. The pre-charge circuitry may be configured to charge the capacitor during a pre-charge mode of the electric power converter. The electric power converter may be configured to exit the pre-charge mode and enter an energy transfer mode responsive to a charge level of the capacitor reaching a threshold pre-charge level.

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a tough object proximate to the element.

Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.

Abstract: According to an embodiment, a semiconductor device includes a differential input circuit suitable for receiving first and second input signals respectively inputted to first and second input transistors, and outputting an output signal; a comparison circuit suitable for generating a first judge signal by comparing the output signal with a first comparison voltage, and generating a second judge signal by comparing the output signal with a second comparison voltage, in a calibration mode; an offset control circuit suitable for adjusting coarse codes and fine codes, according to the first and second judge signals; and an offset adjusting circuit suitable for adjusting a drivability of each of the first and second input transistors by a first strength, according to the coarse codes, and adjusting the drivability of each of the first and second input transistors by a second strength smaller than the first strength, according to the fine codes.

Abstract: Disclosed are a device and a method for calibrating a reference voltage. The reference voltage calibrating device includes a data signal communication unit that transmits/receives a data signal, a data strobe signal receiving unit that receives a first data strobe signal and a second data strobe signal, a voltage level of the second data strobe signal being opposite to a voltage level of the first data strobe signal, and a reference voltage generating unit that sets a reference voltage for determining a data value of the data signal, based on the first data strobe signal and the second data strobe signal, and the reference voltage generating unit adjusts the reference voltage based on the first data strobe signal and the second data strobe signal.

Abstract: Systems and methods for differential data transmission using an unterminated transmission line comprise a plurality of switches configured to control a differential voltage output on a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines. A transition switch with an output impedance equal to that of the output lines will discharge the lines during a state transition so as to reduce to power consumption associated with changing states of the transmission line.

Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.

Abstract: A circuit for controlling a gate driver includes a delay circuit, a first logic circuit, and a second logic circuit. The delay circuit receives a first turn-off signal and produces a second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration. The first logic circuit receives the first and second turn-off signals and produces a smart turn-off signal by asserting the smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted. The second logic circuit receives a restart signal and the smart turn-off signal and produces a smart reset signal by asserting the smart reset signal when the restart signal and the smart turn-off signal are de-asserted, and de-asserting the smart reset signal when one or more of the restart signal and the smart turn-off signal are asserted.

Abstract: The present invention relates to a signal duty cycle adaptive-adjustment circuit and method for a receiving terminal. In one embodiment, the circuit includes an analog level comparison circuit, a preprocessing circuit, a first path switch, a second path switch, a decoding circuit, a parameter extraction and estimation circuit, an error generation circuit, a filter feedback circuit and a digital-to-analog conversion circuit. The analog level comparison circuit receives a valid signal according to a reference level to generate a duty cycle signal. The preprocessing circuit preprocesses the duty cycle signal. When the first path switch is turned on, the parameter extraction and estimation circuit acquires duty cycle information from the duty cycle signal to generate a duty cycle deviation. The error generation circuit processes the duty cycle deviation to generate an error signal.

Abstract: An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vo1+ and Vo1?; and an output alignment circuit configured to output voltages Vo+ and Vo? that are triggered by an edge of a combination of Vo1+ and Vo1?, and where Vo+ and Vo? are set by high states of Vo1+ and Vo1? prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vo1+ and Vo1?; and outputting, by an output alignment circuit, voltages Vo+ and Vo? that are triggered by an edge of a combination of Vo1+ and Vo1?, and where Vo+ and Vo? are set by high states of Vo1+ and Vo1? prior to a transition on an input of the level-shifter circuit.

Abstract: An integrated circuit device includes a read strobe signal transmitter including a main output drive circuit and a victim output drive circuit having an output terminal electrically coupled to an output terminal of the main output drive circuit. The read strobe signal transmitter is configured to: (i) generate a periodic active read strobe signal during a read time interval, in response to a pair of periodic drive signals, which are 180° out-of-phase relative to each other during the read time interval, and (ii) generate a disabled read strobe signal at a fixed logic level during a non-read time interval, in response to an active victim control signal. The main output drive circuit is responsive to the pair of periodic drive signals during the read time interval, and the victim output drive circuit is responsive to the active victim control signal during the non-read time interval.

Abstract: The present disclosure provides an off-chip driver (OCD) and an associated DRAM. The OCD operates in a power domain. The power domain works under a minimum system voltage and a maximum system voltage. The OCD is configured for providing a drive current to an output pad. The OCD includes a pull-push circuit. The pull-push circuit is coupled to the output pad. The pull-push circuit includes a current source circuit. The current source circuit includes a VCCS. The VCCS is configured to provide, in response to an operation voltage, an impedance with respect to the output pad, wherein the operation voltage ranges between the minimum system voltage and the maximum system voltage.

Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

Abstract: A gate driver circuit and a method of operating a gate driver circuit. The gate driver circuit comprising a high auxiliary voltage rail and a low auxiliary voltage rail for receiving high auxiliary voltage and low auxiliary voltage, output stage connected to the auxiliary voltage rails and comprising a control input and an output terminal for providing an output voltage of the gate driver, plurality of series connections of controllable switches and resistive components, wherein a first part of the plurality of series connections is connected between the high auxiliary voltage rail and control input of the output stage, and a second part of the plurality of series connections is connected between the low auxiliary voltage rail and control input of the output stage, and a control circuit for controlling the controllable switches for providing a control voltage and a control current to the control input of the output stage.

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

Abstract: A device and method are disclosed. The device and method allow the clock signal of a wireless communication device to produce an oscillation with a 50% duty cycle. The device and method allows quick convergence to a 50% duty cycle after power up and also provides stability of the duty cycle across variations in ambient temperature and power supply fluctuations. The device includes, but is not limited to a buffer, a first inverter electrically coupled to the buffer, a second inverter electrically coupled to the first inverter, and a differential integrator, wherein a first output of the first inverter is electrically coupled to a first input of the differential integrator, wherein a second output of the second inverter is electrically coupled to a second input of the differential integrator, and wherein a third output of the differential integrator is electrically connected to the buffer.

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

Abstract: Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.

Abstract: A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second data having a second level. The memory apparatus adjusts a level of a reference voltage by comparing the reference voltage with each of the first data and the second data.

Abstract: A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well.

Abstract: Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.

Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.

Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

Abstract: Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.

Abstract: A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A signal level adjustment system adjusting a level of signal outputted from a signal output circuit is realized. An input buffer threshold adjustment unit sets a threshold of a signal input circuit to a first variable value. A signal level adjustment unit adjusts an output level of a first signal at the signal output circuit until a voltage of the first signal outputted from the signal output circuit and inputted to the signal input circuit falls into a given range determined based on the threshold.

Abstract: A circuit arrangement for producing short electrical pulses, including a logic gate (1) with a very short gate transit time and having a clock signal being supplied to a trigger input (2) of the logic gate (1) as a trigger signal. An output signal based on the trigger signal is generated as a short electrical pulse at an output (3) or at one output (3 or 4) or at both outputs (3 and 4) of the logic gate (1).

Abstract: A signal transmission system is provided which is capable of simplifying circuits and shortening time required for automatic adjustment of pre-emphasis. A signal having a single pulse pattern is generated by a single pulse pattern generating circuit. A signal having passed through a selector is divided into two signals whose phases are inverted and which are transmitted to a receiving circuit. An eye aperture of an eye waveform in a direction of time is measured by an eye aperture judging section by using the two signals and a sampling clock output from a sampling clock controlling section. An adjustment controlling section compares the measured eye aperture with a target value for judgment and transmits the judgment result to the transmitting circuit, where pre-emphasis is adjusted based on the judgment result.

Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included.

Abstract: A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again.

Abstract: A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the power source voltage line and the ground line, including at least two second MOS transistors coupled in series. The gate length and the gate width of the first MOS transistor are adjusted so that the first MOS transistor has a gate area allowing a first characteristic variation of the first MOS transistor to be substantially equal to a second characteristic variation of the second MOS transistor.

Abstract: A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: Techniques are provided for synchronizing the data signals transmitted through a synchronous bus in a display device. One embodiment includes manipulating the clock signals and/or data signals transmitted by a display controller in the display based on the location on the bus where a data signal is to be transmitted. For example, a pre-emphasized clock signal having a higher initial voltage level may be used for a data signal transmitted farther on the bus from the display controller. The pre-emphasized clock signal may compensate for propagation delays associated with transmitting the data signal through the bus. Further, a de-emphasized clock signal may be used for data signals transmitted to a section on the bus closer on to the display controller, and neutral clock signals may be used for data signals transmitted to a section that is of intermediate distance from the display controller.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance.

Abstract: A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.