Abstract: An input/output (I/O) circuit for an integrated circuit includes an input-output terminal, a termination circuit and an impedance compensation circuit. The termination circuit includes a node that is coupled to the input-output terminal. The termination circuit exhibits substantially constant first impedance below a first frequency of signals received at the input-output terminal. Furthermore, the termination circuit exhibits second impedance that is less than the first impedance when signals having a second frequency that is higher than the first frequency are received at the input-output terminal. The impedance compensation circuit is coupled to the input-output terminal. The impedance compensation circuit compensates for differences between the first and second impendences when the signal having the second frequency that is higher than the first frequency is received at the input-output terminal.

Abstract: A power switch circuit includes a first input voltage, a first switch element, a switcher, a first bootstrap capacitor, and a second bootstrap capacitor. The first switch element includes a first control end, a first input end, and a first output end. The first input end is coupled to the first input voltage. The first output end provides an output voltage. The switcher is coupled to the first switch element. The first bootstrap capacitor is coupled to the switcher and provides a first driving voltage. The second bootstrap capacitor is coupled to the switcher and provides a second driving voltage. The first bootstrap capacitor and the second bootstrap capacitor alternately supply the first driving voltage or the second driving voltage to the first control end through an operation of the switcher.

Abstract: There is disclosed herein a circuitry system comprising first and second IC chips, configured or configurable such that; the first IC chip has an output terminal connected to receive an output signal from an output-signal unit of the first IC chip, the output-signal unit being connected between high and low voltage-reference sources of the first IC chip, the high and low voltage-reference sources being connected to respective high and low voltage-reference terminals of the first IC chip; and the second IC chip has an input terminal connected in a potential-divider arrangement between high and low voltage-reference terminals of the second IC chip, wherein: the high and low voltage-reference terminals of the first IC chip are respectively connected to the high and low voltage-reference terminals of the second IC chip; and the output terminal of the first IC chip is connected to the input terminal of the second IC chip.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An apparatus comprises multiple impedances and multiple pairs of transistors. Each pair connects to an impedance. Each pair includes high and low side transistors. The high side transistors and the low side transistors are connected each other and to a first terminal of the corresponding impedance, wherein second terminals of the impedances are connected to each other. The apparatus also comprises a staggered signal transistor driver to assert separate delayed high side signals to control inputs of the high side transistors. The delayed high side signals are time delayed with respect to each other. The driver asserts separate delayed low side signals to control inputs of the low side transistors.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a chip section signal and command/address signals. The second semiconductor device may be configured to enter a power-down operation based on the chip section signal and the command/address signals. The second semiconductor device may be configured to interrupt input of a first group of the command/address signals during the power-down operation. The second semiconductor device may be configured to selectively perform an on-die termination (ODT) operation according to a level combination of a second group of the command/address signals.

Abstract: A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

Abstract: A transmitter includes: a driver circuit having a pull-up circuit, and a pull-down circuit, coupled to an output pad; a digitally controlled impedance (DCI) calibration circuit having a first reference driver, a second reference driver, and a reference resistor, the DCI calibration circuit configured to: generate a value for a first code by calibrating a first impedance in the first reference driver against the reference resistor; generate a value for a second code by calibrating a second impedance in the second reference driver against the first impedance; and adjust the value of the first code to match the first impedance with the second impedance; and a pre-driver circuit configured to supply the first code and the second code to the driver circuit for adjusting output impedance of the pull-up circuit and the pull-down circuit.

Abstract: A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.

Abstract: A memory system includes a calibration engine, a memory, and a memory controller coupled to the memory by a channel used to transmit a plurality of commands from the memory controller to the memory. The memory controller estimates a total energy consumed based on the first plurality of commands in a first sampling period and determines a first temperature change of the memory based on the first total energy consumed. The memory controller transmits an impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold. The calibration engine changes an impedance of an I/O terminal of the memory based on the calibration command.

Abstract: A terminal circuit and an output stage circuit are provided. The terminal circuit is configured between a transmitter and an external device. The transmitter provides a differential signal to the external circuit. The terminal circuit includes a first to a third switches and a first and a second resistor. The first switch is biased by a first voltage provided by the transmitter. The first and the second resistor receive the differential signal. The second switch is coupled between the first switch and the first resistor. The third switch is coupled between the first switch and the second resistor. The first to the third switches are controlled by a first to a third control signals, respectively. When the transmitter operates in a power-off mode, a voltage level of the first voltage is in ground level, and the first to the third control signals turn off the first to third switches.

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Abstract: A method and an apparatus for wireless communication are provided. The apparatus having a first latch having a first latch input and first latch output and a second latch having a second latch input, a second latch scan output, and a second latch data output. The second latch input is coupled to the first latch output. The apparatus further includes a selection component configured to select between a data input and a scan input based on a shift input. The selection component is coupled to the first latch input. The selection component includes a first NAND-gate, a second NAND-gate, and an OR-gate.

Abstract: One or more characteristics of devices are ascertained in accordance with one or more aspects of the disclosure. As may be consistent with one or more embodiments, the attachment of an external circuit to an input port is detected based on a resistance value presented by the external circuit. A resistance range that includes the resistance value presented at the input port is determined, in response to detecting the attachment, by dynamically coupling one or more of a plurality of resistor-based circuits relative to the input port. A signal presented by the external circuit on the input port is coded based on the determined resistance range, using one or more of the resistor-based circuits, and the code is used to identify a type of the external circuit. These aspects can provide for the communication of power and data with a variety of different types of external circuits.

Abstract: An insulated gate semiconductor device includes an insulated gate semiconductor element, an output current detection unit, a voltage detection unit, and a heat generation amount suppression unit. The insulated gate semiconductor element on-operates by receiving a first gate voltage at a control terminal, and switches and outputs an input voltage to a load. The output current detection unit detects an output current to the load. The voltage detection unit detects an on-voltage of the insulated gate semiconductor element. The heat generation amount suppression unit sets a gate voltage to be applied to the control terminal of the insulated gate semiconductor element higher than the first gate voltage in response to the output current exceeding a rated current value and the on-voltage being lower than a first threshold voltage.

Abstract: A pull-up leg of disclosed circuitry includes a pull-up pre-driver and a pull-up driver coupled to the pull-up pre-driver. A pull-down leg includes a pull-down pre-driver and a pull-down driver coupled to the pull-down pre-driver. An input/output pad is coupled between the pull-up driver and pull-down driver. A driver-and-termination control circuit is coupled to receive a tristate control signal, a termination control signal, and an input data signal. The driver-and-termination control circuit selects a drive mode, tristate mode, or termination mode in response to the tristate control signal and the termination control signal. The driver-and-termination control circuit drives a first data signal to the pull-up driver and drives a second data signal to the pull-down driver. The first and second data signals have equal logic states in the drive mode and have opposite logic states in the tristate and termination modes.

Abstract: A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage.

Abstract: An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code.

Abstract: The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.

Abstract: A light-emitting diode (LED) driver circuit and a light apparatus including the LED driver circuit are provided. The light apparatus includes an LED array, an input unit, a rectifier, and a control circuit. The LED array includes LED devices connected to one another in series. The input unit receives an alternating current (AC) power source. The rectifier circuit full-wave rectifies the received AC power source signal and supplies the full-wave rectified AC power source signal to the LED array. The control circuit selectively lights the LED devices according to a voltage level of the full-wave rectified AC power source signal. The control circuit includes switching elements and comparators. The switching elements selectively force nodes between the LED devices to be grounded. The comparators turn-on one of the switching elements according to the voltage level of the full-wave rectified AC power source signal.

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

Abstract: A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

Abstract: Apparatus include a data bus and a signal driver circuit having pluralities of first and second termination devices connected in parallel between a voltage node and an output node. Each of the termination devices is configured to be deactivated in response to control signals having a particular set of logic levels, and to be activated in response to control signals having a set of logic levels other than the particular set of logic levels. Activated second termination devices each exhibit respective resistances greater than a particular resistance of each activated first termination device. Methods include connecting a node of an apparatus to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, and comparing a resulting voltage level to a reference voltage different than half-way between voltage levels of the first and second voltage nodes.

Abstract: An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.

Abstract: An electronic device capable of bandwidth compensation includes a register unit for storing a calibration code determined by performing an on-die termination (ODT) calibration process and a data receiving circuit, wherein the calibration code is utilized for controlling a termination resistance of an ODT unit. The data receiving circuit comprises a first control circuit coupled to the register unit and the active low-pass filter for generating a first control signal according to the calibration code stored in the register unit, the first control signal being utilized for adjusting a capacitance of a first feedback capacitor unit or a resistance of a first feedback resistor unit of an active low-pass filter.

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a plurality of second signals by a voltage translation of a plurality of first signals. The second circuit may be configured to switch the second signals to generate a plurality of third signals. The second signals are generally switched such that (i) all third signals are inactive before one of the third signals transitions from inactive to active while a switching condition is enabled and (ii) all third signals are switched inactive while the switching condition is disabled. The third circuit may be configured to amplify the third signals to generate a plurality of output signals. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.

Abstract: In accordance with an embodiment of the invention, the method includes detecting a leaving event such that a communication path established between two peer transceivers coupled to the particular subscriber line is to be orderly discontinued. The method further includes, during a pre-disconnection phase following the detection of the leaving event, switching the two peer transceivers into respective OFF power states during first symbol positions and into respective ON power states during second remaining symbol positions, characterizing crosstalk within the vectoring group during the first symbol positions while the second symbol positions are used for regular data communication if any, and definitively switching the two peer transceivers into the respective OFF power states after the crosstalk characterization completes.

Abstract: A data output circuit includes a data driving unit suitable for driving a data transmission line with a driving voltage corresponding to data during a data transmission operation, and a charging/discharging unit suitable for storing charges on the data transmission line and reuse the stored charges as the driving voltage.

Abstract: Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

Abstract: A calibration circuit for calibrating a device to be calibrated includes a variable current generator, a circuit component, and a control unit. The variable current generator generates a variable current responsive to variations of a supply voltage relative to a predetermined voltage level. The circuit component is a copy of at least one portion of the device to be calibrated and is coupled between the variable current generator and the supply voltage. The control unit is coupled to the variable current generator and the circuit component, and generates, based on a voltage dependent on the variable current and the circuit component, at least one calibration signal for adjusting an adjustable electrical parameter of the circuit component and the device to be calibrated.

Abstract: A tunable microwave network and its application in a radio transceiver transmit signal cancellation network is described. The tunable microwave network realizes a large set of reflection coefficients over a predefined area in the complex reflection coefficient plane for the purpose of reflecting a variable cancellation signal which, when properly configured, results in the substantial attenuation of transmit reflection and transmit leakage signal at the radio transceiver receiver input. A relevant building block of the proposed tunable microwave network is a shunt tunable capacitive element coupled to another shunt tunable capacitive element through a phase shifting element with phase shift greater than 30 degrees divided by a quantity substantially similar to the total number of said tunable capacitive elements and less than 60 degrees at a predefined frequency.

Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.

Abstract: Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system includes a primary transmitter circuit receiving a data signal, a primary transmission line connected to the primary transmitter circuit, and a primary receiver circuit connected to the primary transmission line. The first duplicate transmission system is connected to the primary transmitter circuit, and supplies a transmission timing control signal to the primary transmitter circuit. The primary transmitter circuit stops transmitting (e.g., stops reducing the voltage of the primary transmission line) when the transmission timing control signal is received. The second duplicate transmission system is connected to the primary receiver circuit, and supplies an output timing control signal to the primary receiver circuit, and the primary receiver circuit outputs the data signal when the output timing control signal is received.

Abstract: Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.

Abstract: A light-emitting unit outputs an optical signal corresponding to an input electric signal. A light-receiving unit is electrically insulated from the light-emitting unit and outputs an electric signal according to the received optical signal as an output signal. In the light-receiving unit, a first light-receiving device outputs an optical current according to the optical signal. A second light-receiving device is provided not to receive the optical signal. A current duplication circuit duplicates a current flowing through the second light-receiving device. A current-voltage conversion circuit converts a current, which is generated by subtracting the current duplicated by the current duplication circuit from a current flowing through the first light-receiving device, into a voltage signal. A comparator output a result of a comparison between the voltage signal converted by the current-voltage conversion circuit and a threshold voltage as the output signal.

Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

Abstract: A tester is described having output circuits that are operable in either power mode or driver mode. A switching circuit connects force and sense lines to one of the output circuits when in power mode, or connects the same lines separately to the output circuits when in driver mode. A further configuration allows for power to be provided through the lines separately while detecting a measure of power through each line and correcting for unknown resistances of leads connected to the lines.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Abstract: In one embodiment, an apparatus for transmitting a signal with an improved termination is disclosed. The apparatus includes a driver to generate a differential mode signal superimposed on a common mode signal at a differential driver output of the driver. The differential driver output includes a first driver output and a second driver output. The apparatus also includes a termination circuit coupled between the first driver output and the second driver output. The termination circuit includes a capacitor connected to a node. The termination circuit also includes a first resistor and a first inductive element coupled in series between the first driver output and the node. In addition, the termination circuit includes a second resistor and a second inductive element coupled in series between the second driver output and the node.

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may generate a calibration code by performing an impedance calibration operation, and may generate a correction calibration code by inverting or maintaining logic levels of the calibration code based on the calibration code. The output circuit may generate an output signal based on an input signal and the correction calibration code.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

Abstract: A memory system for a computer is provided as well as a method for integrity testing a memory interface. The memory system includes a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output. The memory system further includes an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to one of the plurality of inputs of the AND gate. The method includes driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes, and determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.

Abstract: A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

Abstract: A termination circuit can include an impedance component. A first port can be configured to be connected to a first node. The first node can be a node of a conductor of a cable. A first end of the cable can be configured to be connected to a signal producing circuit. A second end of the cable can be configured to be connected to a first end of a trace disposed on a substrate of a display device. A second end of the trace can be connected to a display driver integrated circuit (DDIC). The DDIC can lack a termination impedance component internal to the DDIC to provide a line termination function for a serial interface with the signal producing circuit. A second port can be configured to be connected to a second node. The impedance component can be connected between the first port and the second port.

Abstract: A high-power, high-frequency radio frequency power amplifier includes an output stage and a single-phase driver. The output stage is arranged in a Class-D amplifier configuration and includes a first depletion mode field effect transistor (FET), a second depletion mode FET, and a bootstrap path that couples the output of the output stage to the gate of the second FET. The first and second depletion mode FETs are switched out-of-phase and between fully-ON and fully-OFF states, under the direction of the single-phase driver. The single-phase driver directly controls the ON/OFF state of the first depletion mode FET and provides a discharge path through which the input gate capacitor of the second depletion mode FET in the output stage can discharge to turn OFF the second depletion mode FET. The bootstrap path provides a current path through which the input gate capacitor of the second depletion mode FET can charge to turn the second depletion mode FET ON.

Abstract: A power supply device includes a board that includes an input terminal and an output terminal, and converters disposed on the board. The converters are connected with each other in parallel and convert an input voltage input to the input terminal, and output the converted voltage to the output terminal. Each of the converters includes respective one of voltage conversion functional units including respective one of input parts and respective one of output parts, respective one of input line parts connected to respective one of the input parts. Respective one of output line parts connected to respective one of the output parts, and respective one of current adjustment functional units provided in respective one of the output line parts for balancing currents output from the each of the converters provided in respective one of the output line parts.