Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A wave formatter circuit for generating a test signal of predetermined waveform in a repetition rate determined by a pattern cycle of a semiconductor test system includes a timing generator for generating a first clock signal and a second clock signal, a waveform shaper which receives the first and second clock signals for generating a set signal and a reset signal, a flip-flop which generates a test signal of predetermined waveform at the timing determined by the set signal and the reset signal, a pattern generator for generating a test pattern data at the rate of the pattern cycle, a data selector which selects first pattern data and second pattern data from the pattern generator to be supplied to the waveform shaper, an inhibit circuit which receives the first and second pattern data from the data selector and provides an inhibit signal to the waveform shaper to prohibit either one of the first and second clock signals in the same pattern cycle passing through the waveform shaper, where the set signal and

Abstract: A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

Abstract: A method and circuit for reading a memory array by utilizing dual dynamic sense amplifiers. A first and a second dynamic sense amplifier are connected to an input line and complementary input line. A latch and a clocking circuit are also connected to the two dynamic sense amplifiers. Initially, an equilibrating signal is input into both sense amplifiers. A first clocking signal and a first isolating signal are then input into the first dynamic sense amplifier. The first clocking signal enables the first sense amplifier to read the data on the input and complementary input lines, while the first isolating signal isolates the first sense amplifier from the input and complementary input lines. An output is then provided to the latch based upon the data read by the first sense amplifier. A second clocking signal and a second isolating signal are then input into the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines.

Abstract: A type of electronic circuit, called an Application Specific Integrated Circuit (ASIC), is used to customize the functions in a semiconductor chip as defined by a user. ASIC includes a microprocessor, functional inputs and outputs, connection circuits, electronic gates, inhibition gates and links to perform "application specific" operations. The user chooses the functions and the arrangement of the various connection circuits from a menu of predetermined functions. Once the ASIC has been defined by the user, it is ready for manufacturing.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.