Abstract: An apparatus for generating multi-signaling output voltage may include at least one output buffer, wherein the at least one the output buffer may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a Zener diode along with a switchable current source. The apparatus may further include first logic circuitry, second logic circuitry, first voltage down level shifter circuitry, second voltage down level shifter circuitry, and a first voltage up level shifter circuitry. Outputs of the first voltage down level shifter circuitry, the second voltage down level shifter circuitry, and the first voltage up level shifter circuitry are combined using the output buffer to generate the desired output. The second NMOS transistor acts as isolation transistor for reducing and/or preventing diode current between a first supply voltage and the third supply voltage.

Abstract: Disclosed is a mechanism to help a user equipment device (UE) transmit multiple distinct bit streams concurrently to a base station with reduced risk of interference. The UE will orthogonally encode the multiple distinct bit streams using orthogonal binary codes to produce orthogonally encoded bit streams, and the UE will add the orthogonally coded bit streams together to produce a resulting bit stream and will transmit that resulting bit stream on an antenna path to the base station. Upon receipt of the transmitted bit stream, the base station could then apply the same orthogonal binary codes to the bit stream in order to extract the underlying multiple distinct bit streams.

Abstract: A method of making a semiconductor device includes etching an insulation layer to form a plurality of openings over a first region of the substrate and a plurality of openings over a second region of the substrate. The method includes filling a first opening of the plurality of openings over the first region with a first P-metal. The method includes filling a second opening of the plurality of openings over the first region with a first N-metal. An area of the first N-metal substantially differs in size from an area of the first P-metal. The method includes filling a first opening of the plurality of openings over the second region with a second P-metal. The method includes filling a second opening of the plurality of openings over the second region with a second N-metal. An area of the second N-metal differs from an area of the second P-metal.

Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.

Abstract: An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.

Abstract: In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.

Abstract: A switch drive and control arrangement may comprise a first transformer configured to receive a control signal, a second transformer configured to receive a clock signal, and a demodulator configured to receive the control signal and the clock signal from a switch controller, via the first transformer and the second transformer. The demodulator may be configured to output a demodulated signal in response to the control signal and the clock signal. A signal fault detector may be provided to determine a fault in at least one of the control signal and the clock signal. A switch may be turned off in response to a fault being detected in at least one of the control signal or the clock signal.

Abstract: A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire, forming a spacer layer on a portion of the sacrificial cover layer, wherein a portion of the sacrificial cover layer extends above the top surface of the spacer layer, removing the portion of the sacrificial cover layer that extends above the top surface of the spacer layer, forming a gate structure on the spacer layer and a remaining portion of the sacrificial cover layer, forming an interlayer dielectric (ILD) layer on the gate structure, removing the dummy nanowire to form a nanowire trench, and forming a replacement nanowire in the nanowire trench.

Abstract: A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract: A carbon nanotube-based ternary comparator including a first decoder, a second decoder, and a comparison circuit. The comparison circuit includes: a first comparison unit for producing a greater-than-or-equal-to signal, and a second comparison unit for producing a less-than-or-equal-to signal. A first two-bit ternary signal is input into the signal input terminal of the first decoder. A first three-bit binary signal and a phase inverted signal of the first three-bit binary signal are output from a signal output terminal of the first decoder. A second two-bit ternary signal is input into the signal input terminal of the second decoder. A second three-bit binary signal and a phase inverted signal of the second three-bit binary signal are output from the signal output terminal of the second decoder.

Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

Abstract: A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

Abstract: Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: A driving circuit is provided. The driving circuit has: a level shifter configured to receive a reference voltage and an input signal at a first voltage to generate a second voltage; an differential amplifier, coupled to the level shifter, configured to receive the second voltage and an output signal to provide an operating voltage, wherein the differential amplifier is supplied by a first power source at a third voltage; and an output stage, coupled to the differential amplifier, configured to receive the input signal and the operating voltage for switching the output signal, wherein the first voltage is smaller than the third voltage, and the output signal has a fourth voltage between the first voltage and the third voltage.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two.

Abstract: The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and non-connection of the input terminal IN and a second supply VSS are provided. The pull-up switching device and the pull-down switching device are operated exclusively on and off in time division to hold and output the state of the input terminal during each operating state from the two output terminals.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

Abstract: A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and non-connection of the input terminal IN and a second supply VSS are provided. The pull-up switching device and the pull-down switching device are operated exclusively on and off in time division to hold and output the state of the input terminal during each operating state from the two output terminals.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.

Abstract: The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two. A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

Abstract: An integrated circuit (70) includes a first power supply bus (72) and a second power supply bus (74). The first power supply bus (72) provides a first power supply voltage (VDD) to a first plurality of circuit elements (12 and 76). The second power supply bus (74) provides a second power supply voltage (LVDD) to a second plurality of circuit elements (14), where the second power supply voltage is lower than the first power supply voltage. During a normal operating mode of the integrated circuit (70), the first power supply bus (72) provides the first power supply voltage to the first plurality of circuit elements (12 and 76) and the second power supply voltage is not provided to the second plurality of circuit elements (14). During a low power operating mode, the second power supply bus (74) provides the second power supply voltage to the second plurality of circuit elements (14) and the first power supply voltage is not provided to the first plurality of circuit elements (12 and 76).

Abstract: A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driving capacity. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter includes a second transistor having a second current driving capacity smaller than the first capacity. The inversion circuit has an output terminal connected to the first input terminal. The inversion circuit receives an input signal including a first input signal and a second input signal one of which is a one-shot pulse signal. The inversion circuit includes a third transistor having a third current driving capacity smaller than the first capacity and larger than the second capacity.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A tri-level decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is configured to compare an input voltage to a first threshold, and the second decoder circuit is configured to compare the input voltage to a second threshold. The first decoder circuit is configured to provide substantially no current to a current mirror if the input voltage is less than the first threshold, and to provide a current to the current mirror otherwise. The current mirror is configured to reflect the current to provide a reflected current. A current source is configured to pull down a first output node to a first logic level if the reflected current is substantially zero. The current mirror is configured to drive the first output node to a second logic level otherwise. The second decoder circuit may operate similarly.

Abstract: An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of ?V, includes a plurality of field effect transistors for driving the output by supplying or removing a current to or from the output, with the relationship of the channel widths of at least two field effect transistors, which both function either to lead a current to or away, being set in dependence on the value of the voltage difference.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A simultaneous bi-directional signal transmission system includes a first semiconductor device, a second semiconductor device, and one or more transmission lines. The first semiconductor device includes a first output MUX which receives first binary data and converts the first binary data into a first signal having one of at least four levels; a first transmitter which is connected to the first output MUX and outputs the first signal via the transmission line to the second semiconductor device; a first receiver which compares one or more reference voltages selected by the first signal with a third signal input via the transmission line and outputs the comparison result; and a first input encoder which detects the second binary data based on the comparison result output from the first receiver.

Abstract: The invention relates to a device for receiving digital signals on the basis of two different standards conveyed on the same medium. A logic-level conversion device receives the digital signals and converts their logic levels into logic levels on the basis of a single standard. Reception is provided for receiving signals coded on the basis of a first standard, which signals are output by the logic-level conversion device. Signals coded on the basis of a second standard are converted into signals coded on the basis of the first standard, which signals are output by the logic-level conversion device. Signals are transferred which are output as converted signals coded on the basis of a second standard into signals coded on the basis of the first standard to the reception device upon reception of signals coded on the basis of the second standard, or for transferring signals output by the logic-level conversion device upon reception of signals coded on the basis of the first standard.