Abstract: A level shifter applied to a driving circuit of a display is disclosed. The level shifter at least includes a first stage of level shifting unit, a second stage of level shifting unit, and two third stage of level shifting units belonging to different power domains and used to perform boost conversion of voltage signals in different power domains. The first stage of level shifting unit includes eight transistors. The second stage of level shifting unit includes four transistors. The two third stage of level shifting units both include six transistors and two output terminals. The level shifter of the driving circuit in this invention makes the output terminals of the two third stage of level shifting units belonging to different power domains to synchronously output the voltage-shifted voltage signals.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: A signal buffer circuit includes a buffer to conduct a buffering operation for transmitting a signal to a subsequent unit; a resistor connected between an input side and an output side of the buffer; and a variable impedance device connected in series to the output side of the buffer. The variable impedance device is at low impedance when the buffer is conducting the buffering operation and at high impedance when the buffer is not conducting the buffering operation.

Abstract: A switched-mode level-shifter shifts a differential voltage superimposed on a common-mode voltage. In the level shifter, a common-mode inductive reactor has at least two windings, and at least one of the differential voltage and the common-mode voltage are applied to at least one of the windings of the reactor. A switch charges the inductive reactor when caused to be in a first state, where the inductive reactor when charged experiences a change of flux according to the applied voltage. The switch also actuates a reset of the charged inductive reactor when caused to be in a second state, where the inductive reactor when reset reverses the change of flux experienced thereby. A source of a chopping signal is provided to alternately drive the switch between the first and second states, where each of the first and second states is one of in and out of conduction.

Abstract: A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

Abstract: A high voltage control circuit of a semiconductor device includes an output node control circuit configured to set an initial potential of an output terminal or to discharge the potential of the output terminal, in response to an input signal and a high voltage supply circuit comprising an acceleration unit and a potential control unit coupled in series between the output terminal and a supply terminal for supplying a high voltage. The acceleration unit is operated in response to the potential of the output terminal, and the potential control unit is operated in response to the input signal.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.

Abstract: Some of the embodiments of the present disclosure provide a method comprising providing an integrated circuit with a level shifting circuit having a pull up device that is configured to selectively pull up a voltage level of an output signal from a low voltage level to a high voltage level, and having a pull down device that is configured to selectively pull down the voltage level of the output signal from the high voltage level to the low voltage level; ascertaining a high level of an input control signal; and when the output signal is at the high voltage level, deasserting the pull up device. Other embodiments are also described and claimed.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Abstract: A producing method of producing a solid state pickup device is provided. Imaging elements are formed on a wafer in a matrix form. Each of the imaging elements has a light receiving surface and plural contact points. Receiving surface border portions are formed on a glass plate to protrude therefrom in a matrix form by etching. The receiving surface border portions are attached to the wafer to surround the light receiving surface in each of the receiving surface border portions. The light receiving surface is spaced from the glass plate. The glass plate is diced outside respectively the receiving surface border portions, to form shield glass for covering the light receiving surface. The wafer is diced for each of the imaging elements, to obtain the solid state pickup device having the shield glass and one of the imaging elements.

Abstract: An electric charge transfer apparatus comprises a plurality of vertical charge transfer devices, each of which transfers a signal electric charge, a plurality of charge-discharging circuits formed next to each vertical transfer device, each charge-discharging circuit discharging the signal electric charge transferred by at least either one of the adjoining vertical transfer devices, and an output circuit that outputs the signal electric charge transferred by the vertical charge transfer devices to an outside of the electric charge transfer apparatus. Appearance of a longitudinal line caused by left-behind electric charge which causes an electric potential barrier or an electric potential unevenness which exists in a transfer channel of a vertical electric charge transfer device included in an charge-discharging device with probability can be controlled.

Abstract: In a charge transfer device and a driving method therefor, electrons are injected through an insulating film into floating gate 108 or electrons are extracted through the insulating film from the floating gate 108, whereby the potential of the floating gate is converged to a fixed voltage.