Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in response to an adjustable balance point of the input request signals, where the balance point is adjusted to reduce a metastable state of the first circuit.

Abstract: A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Abstract: A synchronous circuit comprising a first flip-flop which has a first clock input terminal inputting an input signal, a first output terminal outputting a first output signal based on the input signal, a second output terminal outputting a second output signal based on the input signal and a first data input terminal inputting the second output signal; a second flip-flop which has a second clock input terminal inputting a clock signal, a reset terminal inputting a reset signal, a third output terminal outputting a third output signal based on the clock signal and the reset signal, a fourth output terminal outputting a fourth output signal based on the clock signal and the reset signal and a second data input terminal inputting the fourth output signal; a third flip-flop which has a third clock input terminal inputting the third output signal of which voltage level is reversed, a fifth output terminal outputting a fifth output signal based on the reversed third output signal, a sixth output terminal outputting

Abstract: A dynamic semiconductor integrated circuit is provided, in which an operation speed is increased, an operation is stabilized, and low power consumption is realized in a system where a NAND dynamic circuit is connected to a NOR dynamic circuit. A compensating circuit is provided, which compensates for a voltage drop at an output node of the NOR dynamic circuit due to a coupling capacitance formed between the output node of the NOR dynamic circuit and an output node of the NAND dynamic circuit, caused when the output node of the NAND dynamic circuit is discharged while the output node of the NOR dynamic circuit holds a charge.

Abstract: Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

Abstract: Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failure. In particular, the invention addresses the synchronization failure problem and the lack of a metastable state in prior art synchronizers. Prior attempts have shown that the conditions rex and rex (where re is the control input and x is the data input) cannot be arbitrated. To overcome this, embodiments of the present invention introduce explicit signals a0 and a1 to hold the values rex and rex, respectively. One embodiment is a fast synchronizer. It has four main components—an input integrator, an inverting component, a SEL component and an output filter. Another embodiment of the present invention is a safe synchronizer that meets the strictest QDI design requirements. Other embodiments use a standard arbiter and a killable arbiter for arbitration.

Abstract: An apparatus includes a first latch having an output terminal. A latch signal is received by the first latch. A second receives the latch signal and having an input terminal coupled to the output terminal of the first latch. A delay circuit delays the latch signal to the first latch.

Abstract: A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch 209. Detection logic 202a,b 703 detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch 209. Suppression logic 703 generates an output of a selected logic level in response to the detection of a metastable state by detection logic 702/703.

Abstract: A method of using low voltage-swing clocks (512) with CMOS latches (502-522, 504-524) and with bi-CMOS latches (904-914, 906-916) and associated circuit structures to reduce power requirements of these circuits compared to conventional CMOS and bi-CMOS circuits. Also, a method of using low voltage-swing clocks (1136) to control CMOS (FIG. 11) and bi-CMOS dynamic logic. The power consumption of CMOS and bi-CMOS microprocessors and other chips can be substantially reduced by using low voltage-swing clocks, with savings of up to 60% to 80% of the normal clock power at speeds comparable to using normal latches and dynamic logic gates, with noise margins sufficient for safe operation.

Abstract: A circuit for reducing the noise associated with a clock signal for a latch based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a predetermined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: A system 400 and method 1200 is disclosed for a fast locking (e.g., within 1.5 sync bit times or the first data transition) clock and data recovery (CDR) system used in high speed data communications applications (e.g., ASIC and microprocessor chips). The CDR circuit takes multiple (e.g., 8) phases of the local clock, which are offset (e.g., by 45 degrees), and uses the multiple phases to latch the state of data at multiple times, and uses the latched data to determine which of the multiple phases captured a data transition. The CDR circuit compares the indicated phase to the phase used to capture a previous data transition and uses such information to, produce a stable selection of a clock phase. The selected clock phase is then employed to provide a recovered clock and data signals (CLK_OUT, and DATA_OUT), in association with the incoming serial data stream independent of jitter and free of metastable conditions.

Abstract: An apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs.

Abstract: An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

Abstract: An apparatus comprising an arbiter cell and a delay logic circuit. The arbiter cell may be configured to receive a plurality of request signals and provide two or more grant signals. The delay logic circuit may be configured to interface the arbiter cell and force each of the plurality of request signals to be serviced in succession when a metastable state occurs.

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: The present invention presents an anti-meta trap (AMT) circuit for maintaining the data integrity of transmitted bit data in various applications. The anti-meta trap (AMT) circuit implement bit data integrity checks to prevent bit data from being misinterpreted at the bit level, that is, from being sampled at a data transition state. The invention also presents an anti-meta circuit combined with an auto-synchronization circuit to synchronize the phase of complete, bit-data verified cells, e.g., ATM data cells. The combined AMT-ASC is therefore able to verify the integrity of the data at the bit level, and synchronizing fixed-length data cells.

Abstract: One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage.

Abstract: A synchronizing stage for synchronizing asynchronous signals provides for a signal stage to be connected in parallel with a clocked input stage and a holding stage that is clocked in anti-phase. The signal stage is clocked in anti-phase with the input stage. An output stage is connected downstream of the parallel circuit. The synchronizing stage reduces the probability of a metastable state in the event of overlapping and non-overlapping clock signals and ensures the reliable transfer of an input datum to the output of the synchronizing stage.

Abstract: A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit.

Abstract: A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Abstract: A control circuit for clock enable staging between first and second clock macros wherein each clock macro produces a clock signal at an output in response to a transition of a global clock signal when an enable signal has been activated. The control circuit comprises a latch element having a first input coupled to the output of the first clock macro, a second input of the latch element is coupled to the output of the second clock macro, and an output node coupled to the enable input of the second clock macro. The output node of the latch element activates the enable input of the second clock macro responsive to the clock signal at the output of the first clock macro, and inactivates the enable input of the second clock macro responsive to the clock signal at the output of the second clock macro.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Abstract: The present invention provides a level sensitive circuit connected to the output portion of a register, which synchronizes an asynchronous input to a clocked network driven by the CPU system clock. The level sensitive circuit ensures that the output of the synchronizing register will always be a definite binary signal, i.e. logical 0 (ground, or absence of voltage) or logical 1 (voltage). The present invention not only minimizes the occurrence of a metastable condition, but also recognizes that metastability may occur. The present invention is optimized to prevent metastability and includes a synchronizing latch having an output circuit with a feedback mechanism that effectively causes the output voltage of the register to be a valid signal only when any metastable condition has resolved itself. More particularly, the non-inverted output of the register is utilized as feedback to the level sensitive circuit.

Abstract: A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data.

Abstract: An apparatus and method for controlling and rectifying possible metastability situations having a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit having an input circuit coupled to the first circuit and receiving signals therefrom. A control circuit for controlling possible metastability situations arising in communication between the first circuit and the second circuit is also provided. The control circuit receives as input the first clock signal and the second clock signal and provides a shifting of at least one of the two clock signals, in such a way that a possible metastable state of the input circuit is avoided.

Abstract: A circuit and method for improving the metastable resolving time in low-power multi-state devices, including binary latches in integrated circuits. Upon detection of a metastable condition at the outputs of the integrated circuit, an increase in energy is locally applied to the decision making portion of the circuit. The localized application of energy to the decision making circuit reduces the metastability time constant tau (.tau.), thereby causing the circuit to resolve more rapidly to a stable operating state.

Abstract: A metastableproof flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input value formerly received by the flip-flop. In order to make the flip-flop metastableproof, the transition in the output value is delayed when the input value is in a metastable state. When the input value is no longer in the metastable state, then the transition in the output value is allowed to complete.

Abstract: A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected.

Abstract: Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

Abstract: A data transfer circuit device including a data transfer circuit, a latch control circuit and a data latch circuit. The data transfer circuit outputs data therefrom in response to an externally supplied transfer signal. The latch control circuit generates a data latch signal, based on the transfer signal and a latch control signal. The data latch circuit latches the data supplied from the data transfer circuit, based on the data latch signal, and outputs the latched data as output data. When the data is being switched, the latch control circuit prevents the data latch signal from being supplied to the data latch circuit.

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired.

Abstract: A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first digital subsystem and a second digital subsystem is disclosed. The synchronizer circuit includes a master synchronizer cell and a slave synchronizer cell for handling data transfer from the first subsystem to the second subsystem. Each synchronizer cell includes a signal node, a discharge node, a first discharge patch and a second discharge path, both coupled between the signal node and the discharge node, and a control element coupled to the first discharge path and the second discharge path. The control element selectively activates the first discharge path and the second discharge path in response to an input signal.

Abstract: A circuit is provided for filtering asynchronous metastability. The circuit includes two or more output lines that provide signals indicative of the assertion of control or data input signals at a plurality of input lines. Despite the simultaneous assertion of two or more input signals, the circuit prevents the simultaneous assertion of more than one output signal, thereby preventing adverse effects within a digital system connected to the circuit.

Abstract: A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period.

Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

Abstract: A method of compensating a phase of a system clock for use in a system clock circuit for receiving an external clock to produce a system clock for an information processing system, in which the quantity of phase variation of the external clock supplied from a reference clock oscillator provided outside the system is detected; in accordance with the detected quantity of phase variation, the phase variation of the external clock supplied from the reference clock generator is compensated to supply the compensated external clock to the system clock circuit; whether or not a state of the external clock supplied from the reference clock oscillator provided outside the system is abnormal is detected; and in accordance with the detected state of the external clock, one of the external clock supplied from the reference clock oscillator and the compensated external clock is selected to supply the selected external clock to the system clock.

Abstract: A clocking scheme provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node. The precharging delay is achieved by introducing the delay in the clocking circuitry which activates the precharging of the domino node. No delay is introduced in the data path in order not to delay the evaluation and transmission of the data signal. During one phase of a clocking cycle, the domino node is precharged to a predetermined logic state. Also during this precharge phase, an input latch couples an input data signal to the domino circuit. During the other phase of the clocking cycle, the domino circuit performs a logic operation based on the input signal. Also during this evaluation phase, an output latch latches the logic state of the domino output for transmission from the output latch.

Abstract: An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit shifts the average DC level of the CMOS level signals in a positive direction to avoid signal undershoot. An AC peak detection circuit is connected to the inactive leg of the RF transformer to monitor toggling of the ECL level input signal lines. A DC comparator circuit compares the detected peak voltage with a predetermined threshold voltage, and generates an alarm signal representing a toggle-fault whenever the detected peak voltage is lower than the predetermined threshold.

Abstract: A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

Abstract: The present invention relates to a signal detector capable of accurately and reliably interpreting different logic states of an asynchronous signal of unpredictable pulse width or amplitude. In one embodiment of the invention, a meta-stable resistant set-reset (RS) flip-flop is described which can be designed from standard library components suitable for implementation in a cell-based or gate array integrated circuit.