Abstract: Provided is a three-dimensional measurement device applicable to a machining machine. A sensor head contains a body and a collet chuck. A light emitting window and a light receiving window are provided on the front end of the body. A non-contact sensor is incorporated in the body. Laser light emitted by the non-contact sensor is radiated onto a workpiece through the light emitting window. Laser light reflected from the surface of the workpiece is received by the light receiving window. A collet chuck is attached to the rear end of the body. The collet chuck has the same shape as a collet chuck provided by each tool housed in a tool magazine of a machining center.

Abstract: A drive circuit for a display apparatus includes: a switching module, including a first input end, a second input end, a control end, and an output end, where the first input end obtains a first signal, the second input end obtains a second signal, the output end is connected to a pixel electrode, the control end obtains a control signal, the switching module selectively outputs the first signal and the second signal to the output end according to a level change of the control signal; and a controller, connected to the control end, and including a first end and a second end, where the first end obtains a first input signal, the second end obtains a second input signal, and the controller outputs the first input signal according to a period change of the second input signal, to serve as the control signal.

Abstract: A system for controlling a flow rate of a fluid through a valve includes a controller. The controller is configured to receive a raw flow rate measurement from a flow rate sensor assembly configured to measure the flow rate. The controller is further configured to apply a flow rate measurement filter to the raw flow rate measurement to generate a filtered flow rate measurement. The controller is further configured to control actuation of an actuator configured to change the flow rate using the filtered flow rate measurement. The controller is configured to automatically adjust the flow rate measurement filter in response to detecting an event that causes stoppage of the actuation of the actuator.

Abstract: A memory element is provided in which a logical state can be securely stored in all conditions even when input set and reset signals are overlapping. This is achieved through provision of an array of persistence latches with an asynchronous circuit that ensures correct operation. The persistence latches provide a persistent output for each of the first and second edges of each input. The memory element is arranged to receive a plurality of inputs including a first and second input. Each first and second inputs include a digital signal that can transition between a first state via a first edge which triggers transition from the first state to the second state and a second edge which triggers transition from the second state to the first state.

Abstract: A light emitting element emits a modulated light modulated in a pattern having a repetitive period toward a space. A driving unit drives the light emitting element. A light receiving element distributes charges corresponding to an incident light containing a reflected light obtained by reflecting the modulated light on an object to storage capacitors and stores the distributed charges. A control unit controls an exposure of the light receiving element. A signal processing unit measures a distance to the object by using a value sampled by the light receiving element. The control unit controls the exposure of the light receiving element to give a sensitivity to at least one high-order harmonic. The signal processing unit linearly combines a component of a fundamental wave with a component of the at least one high-order harmonic to measure the distance to the object.

Abstract: Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.

Abstract: A differential switch circuit includes: a first transistor having a first terminal coupled with a first input terminal, a second terminal coupled with a first output terminal, and a control terminal coupled with a switch signal receiving terminal; a second transistor having a first terminal coupled with a second input terminal, a second terminal coupled with a second output terminal, and a control terminal coupled with the switch signal receiving terminal; a central switch element positioned between the control terminals of the first and second transistors; and a switch element control circuit for controlling the central switch element based on a switch signal. When the switch signal turns on the first and second transistors, the switch element control circuit turns off the central switch element, and when the switch signal turns off the first and second transistors, the switch element control circuit turns on the central switch element.

Abstract: A semiconductor integrated circuit includes a first circuit configured to provide a predetermined function and a second circuit configured to have a physically unclonable function, wherein the second circuit is incorporated into the first circuit such that a signal value of at least one node in the first circuit varies in response to an output of the second circuit, and the output of the second circuit is set such that the first circuit provides the predetermined function.

Abstract: Methods and systems for enabling coexistence of multiple potentially interfering wireless components in a device are provided. A device may include a wireless module using a proprietary protocol and one or more modules using standardized protocols. The device further includes a coexistence arbitration module configured to arbitrate access to a shared communication medium among the wireless modules based on assertion of medium access requests by the modules and the associated priority of the asserted medium access requests. When multiple medium access requests have the same priority, precedence for access to the shared medium is determined based on additional criteria. The coexistence arbitration module may be a separate module or may be integrated into another module or distributed among the modules. The device may include a host processor for altering transmission characteristics of a module to increase the likelihood that another module can receive data within a reasonable time period.

Abstract: A detecting circuit and a configuration status detecting method of a Real-Time Clock (RTC) battery and an electronic apparatus using the same are provided. The detecting circuit includes a power capturing unit, a voltage dividing unit and an output unit. The power capturing unit couples to a power supply output terminal of the RTC battery and captures a power supply signal from the power supply output terminal in response to a detecting-controlled signal. The voltage dividing unit couples to the power capturing unit and is configured to divide the power supply signal captured by the power capturing unit to generate a dividing signal. The output unit couples to the voltage dividing unit to receive the dividing signal, where the output unit generates a detecting result signal related to a configuration status of the RTC battery according to the dividing signal.

Abstract: A signal processing apparatus and a method are disclosed, in which the signal processing apparatus may convert an analog signal to a digital signal and store the digital signal. The signal processing apparatus may convert analog signals, transmitted by multiple analog channels, to digital signals using analog-to-digital converters (ADCs), hold the digital signals for a predetermined holding time, sequentially read the held digital signals for each digital channel, and store the sequentially read digital signals.

Abstract: A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized.

Abstract: A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

Abstract: A counter counts the run lengths of a binarized signal. A counting result correcting portion generates frequency distributions for run lengths for first run lengths, which are from a rising edge to a falling edge of the signal, and second run lengths, which are for a falling edge to a rising edge of the signal, calculates a total number of first run lengths of lengths that are no less than 0 times and less than 1 times a representative value for the first run lengths, calculates a total number of second run lengths of lengths that are no less than 0 times and less than 1 times a representative value for the second run lengths, calculates a total number of first run lengths, calculates a total number of second run lengths, and corrects the counting results.

Abstract: The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

Abstract: A pulse signal generating device includes: an encoder that outputs a pulse with a period corresponding to the speed of an object to be detected; a measurement unit that measures a period of the pulse; a storage unit that stores the measured period; an operation unit that calculates a reasonable period, which is estimated to be statistically reasonable, on the basis of a result of period measurement of a plurality of pulses; a detection unit that detects period abnormalities when the measured period of the measurement unit satisfies a period abnormality condition specified from the reasonable period; and a pulse generating unit that generates a pulse on the basis of the measured period when the period abnormalities are not detected and generates a pulse on the basis of the reasonable period when the period abnormalities are detected.

Abstract: In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can prevent metastable states of latch output signals from propagating through to output signals (BUSY2 and BUSY1). In addition, filter section (104) can generate output signals (BUSY2 and BUSY1) having one set of values when both inputs are inactive, and a second set of values when latch (102) is in the metastable state.

Abstract: An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit (110) can activate a feedback signal (fb) after a predetermined delay (?), provided both output signals (Sel_A and Sel_B) remain inactive.

Abstract: Calibrating return time includes determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices, storing clock calibration information with respect to each of the slave devices with which the master device will communicate using a bus, and, after the clock calibration information has been stored, resynchronizing data signals that are received from each of the slave devices based on the corresponding stored clock calibration information.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in response to an adjustable balance point of the input request signals, where the balance point is adjusted to reduce a metastable state of the first circuit.

Abstract: In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit.

Abstract: An arbiter that includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs of the second SR type flip-flop indicate which of the two input. signals changed first. The phase comparator can enter a metastable state. The first flip-flop reduces the magnitude of signal swing away from the power supply rails caused by the metastable state. The second flip-flop prevents any signal swing away for a power supply rail is not propagated to an output.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: An asymmetric arbiter provides a fast signal path and a slow signal path. Signals may travel over the fast signal path in substantially less time than it takes for the signals to travel over the slow signal path. The fast signal path may be configured so as to impart only a minimal amount of delay. Signals that are to be frequently arbitrated by the arbiter may be applied to the fast signal path so as to minimize the delay introduced by the arbiter. The arbiter may include circuitry for detecting metastable conditions.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: An active/stand-by determination method for use in a duplicated system, wherein two elements, one given a priority and the other not given a priority, in the duplicated system operate in an active mode and a stand-by mode alternatively by using an X.sub.-- ACTIVE signal, a S.sub.-- ACTIVE signal, a STATUS signal for each element and a SIDE signal, the method comprising the steps of: a) setting both the elements in the stand-by mode upon power-on; b) checking the X.sub.-- ACTIVE signal and the STATUS signal at both the elements; c) entering into the active mode if it is determined at the step b) that both the X.sub.-- ACTIVE signal and the STATUS signal are "high"; d) remaining in the stand-by mode if it is determined at the step b) that at least one of the X.sub.

Abstract: A circuit for power arbitration, low battery voltage detection, and the operation of battery backed circuitry for systems in which the system power supply voltage range overlaps that of a battery source. A voltage regulator is used to regulate the battery voltage so that the voltage range of the battery source is below the voltage range of the system supply. The regulator is based on a silicon-bandgap referenced methodology and consumes an insignificant amount of current so that the battery life is not appreciably affected. The regulator also has a smaller variation in its output voltage than the battery. A temperature and supply voltage compensated voltage is produced by the combination of a subthreshold current source, parasitic bipolar devices, and voltage buffering, and used to provide a voltage source for the battery backed circuitry of the system. The regulated voltage is set to a value lower than the system supply and serves as the battery supply input for the power arbitration circuitry.

Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: An interconnecting network comprising operational amplifiers, summing ampiers, and hysteretic coupling circuits is disclosed. The interconnecting network responds to signals of interest that may be substantially simultaneously present, but only to the highest initial intensity thereof so as to provide priority decoding of signals of interest. The hysteretic coupling circuit has a selectable coupling rate and a selectable coupling constant that allows the hysteretic circuit to respond in a stable so called "winner-take-all" manner, or conversely in a non-stable chaotic manner.

Abstract: A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input. Logic gates are respectively associated with each considered signal and are connected to indicate whether the considered signal is the first or the last activated signal when the flip-flops associated with all the pairs of signals including the considered signal are at respective suitable states once the first or last signal is activated.

Abstract: A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer .gtoreq.2), coupled in a point-to-point configuration. Each module is associated with an input/output port that can communicate with the bus. Each module has an output port (Dout), and arbitration ("ARB") port, and X input ports ("LOCALout", "Din1", "Din2", . . . "Din[X-1]"). The Dout output port of an M.sub.i module is coupled, via a portion of conductive bus, to [X-1] input ports on an adjacent D.sub.i+1 module. Thus, module M.sub.0 's Dout.sub.0 output port is coupled to [X-1] input ports on module M.sub.1, module M.sub.1 's Dout.sub.1 port is coupled to [X-1] input ports of module M.sub.2, and so forth. The modules are X:1 in that the output port of each module is coupled to a chosen one of that module's X INPUT ports, as determined by the state of an arbitration select signal (ARB) coupled to the module's arbitration port.

Abstract: A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.

Abstract: An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memories, a receiving circuit 10(i) and an arbitration circuit 12(i) with standardized configurations are allotted. Common memory cycle clock pulse ARB-CLK is sent from memory cycle generator 16 to all of arbiter units 14(1)-14(N) . From the arbiter units 14(1)-14(N) , the commands for the respective memories are output in synchronization to each other based on memory cycle clock pulse ARB-CLK.