Abstract: A method for cartesian (IQ) to polar phase conversion includes: converting a first input value into a first absolute value, and a second input value into a second absolute value; converting the first absolute value into a first logarithmic value by calculating a scaled logarithmic value of the first absolute value, and the second absolute value into a second logarithmic value by calculating a scaled logarithmic value of the second absolute value; subtracting the first logarithmic value from the second logarithmic value, to provide a subtract value; and selecting a phase value from a plurality of phase values stored in a storage unit. Each of the plurality of phase values corresponds to a respective index value, and the phase value is selected taking the subtract value as the index value.

Abstract: A low-power double-quadrature receiver is disclosed. The double-quadrature receiver includes a quadrature signal generator configured to generate a first quadrature signal and a second quadrature signal based on each component of a differential input signal, and a switching stage configured to perform down-conversion on the first quadrature signal and the second quadrature signal.

Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

Abstract: The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.

Abstract: A frequency shifter configured to shift the frequency of a signal, the frequency shifter comprising: a resonant structure configured to mechanically resonate at a first frequency; and a plurality of capacitors, each capacitor having a variable plate separation distance, wherein the resonant structure is configured to cause the plate separation distance of each capacitor to oscillate so as to cause the frequency of the signal to shift by the first frequency.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: A frequency and phase conversion circuit and wireless communication unit for supporting a plurality of different duty cycles is described. The frequency and phase conversion circuit comprises: a local oscillator module comprising a plurality of frequency conversion modules arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals; and at least one frequency conversion module comprising a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal, wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection circuit includes a multiplier circuit configured to multiply a first voltage signal by a second voltage signal. The multiplier circuit receives the first voltage signal at gates of a first transistor pair and receives the second voltage signal at gates of second and third transistor pairs. In some embodiments, a drain of a first transistor in the first transistor pair is coupled to sources of the second transistor pair, and drain of a second transistor in the first transistor pair is coupled to sources of the third transistor pair. In some embodiments, the power detection circuit includes a comparison circuit that compares the first pair of currents and a second pair of currents associated with a threshold voltage signal.

Abstract: An impedance transformer for use with a quadrature passive mixer is disclosed. In an exemplary embodiment, an apparatus includes a mixer configured to generate an up-converted signal at a mixer output port in response to local oscillator (LO) signals, and an impedance transformer configured to provide a complex impedance at the mixer output port. The complex impedance configured to generate a selected level of the reverse isolation for the mixer thereby generating a selected amplitude flatness symmetry characteristic for the up-converted signal.

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract: A frequency mixer circuit includes a mixer, a load stage, and again stage. The load stage cooperates with the mixer to generate a differential output voltage signal with a mixed frequency according to a differential local oscillator voltage signal and a differential input voltage signal. The gain stage has a transconductance, and a magnitude of the differential current signal and the transconductance have a positive relationship therebetween, so as to result in a positive relationship between the transconductance and a conversion gain which is a ratio of magnitude of the differential output voltage signal to magnitude of the differential input voltage signal.

Abstract: A frequency mixer is disclosed. In an implementation, the multi-LO band switched-core includes a single field-effect transistor (FET) ring having a first mixer core and a second mixer core. The first mixer core and the second mixer core configured to connect to a radio frequency (RF) port and an intermediate frequency (IF) port. The frequency mixer also includes a first local oscillator (LO) transformer and a second LO transformer. The first LO transformer is configured to furnish a first LO signal occurring in a first limited range of frequencies to the first mixer core, and the second LO transformer is configured to furnish a second LO signal occurring in a second limited range of frequencies to the second mixer core.

Abstract: One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33? percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33? percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals.

Abstract: A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: A frequency quadrupler comprises a balanced topology which increases broadband odd harmonic suppression. The frequency quadrupler is constructed in a cascode configuration which is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. The cascode is constructed with common emitter (CE) and common base (CB) stages which further improves the multiplier frequency response. The cascode configuration enables a notch filter to be placed between the common emitter and common base stages to reduce 2nd harmonic generation and thereby increase 4th harmonic output power, generation efficiency and conversion gain. To cancel 4th harmonic components at the input that may destructively interfere with the output signal, capacitors are placed at the input of the common emitter stage, which in conjunction with the parasitic base wire inductance, form a notch filter to short the 4th harmonic.

Abstract: A current-mode analog computational circuit can be controlled to produce multiplying, squaring, divider and inverse functions and corresponding current outputs. The current-mode analog computational circuit is based on an implementation using MOSFETs operating in a sub-threshold region as can provide relatively ultra-low power dissipation. Furthermore, the current-mode analog computational circuit can be operated from a ±0.75 V DC supply. Tanner simulation results conducted using a 0.35-?m TSMC CMOS process confirmed the functionality of the multiplying, squaring, divider and inverse functions of the circuit. The current-mode analog computational circuit advantageously can have a total power consumption of 2.3 ?W, a total harmonic distortion is 1.1%, a maximum linearity error of 0.3% and a bandwidth of 2.3 MHz.

Abstract: According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum.

Abstract: A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time.

Abstract: A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33 ? percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the 1-0 image and even order harmonics.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: A down-frequency conversion circuit and up-frequency conversion circuit, and a receiver and transmitter applying the same are provided. The down-frequency conversion circuit includes a harmonic mixer and general mixer, and thus becomes able to convert frequency using one LO (Local Oscillator) frequency, thereby reducing burden on generating LO frequency.

Abstract: A mixer circuit includes: a mixer circuit including a first transistor pair to output a first differential input signal and a second transistor pair to output a second differential input signal by inversing the first differential signal; a local signal supply circuit to supply a pair of local signals to gates of the first transistor pair and the second transistor pair; an operational amplifier including an input pair coupled to an output pair of the mixer circuit and an output pair coupled to the input pair via feedback resistors, the operational amplifier to amplify the first differential input signal and output a differential output signal; a common mode feedback circuit to control a center voltage of the differential output signal so that the center voltage maintains a common voltage; and a common voltage generator circuit to generate the common voltage according to an amplitude of the local signal.

Abstract: Heterodyne commutating apparatuses and methods for creating the heterodyne commutating apparatuses are disclosed. The heterodyne commutating mixer includes a plurality of switches for transferring a radio frequency input signal sequentially during a plurality of local oscillator period timeslots to a plurality of output capacitors. The heterodyne commutating mixer also includes a plurality of inductors added across differential in-phase output terminals and quadrature output terminals. Values of inductance and capacitance are set to achieve resonance at an output intermediate frequency.

Abstract: In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.

Abstract: A frequency up and down converter, in which, when down converting a high frequency signal into an intermediate frequency signal or up converting an intermediate frequency signal into a high frequency signal by controlling switching elements using a local oscillator signal, a signal with a frequency to be converted is controlled a number of times during one cycle of the local oscillator signal, whereby the local oscillator signal with a frequency lower than an original frequency may be used. Transistors are added in parallel to switching transistors disposed in a frequency down conversion unit or a frequency up conversion unit, and local oscillator signals with predetermined phases and pulse widths are provided to the gates of the transistors such that a high frequency signal or an intermediate frequency signal is transferred to an output terminal at least two times during one cycle of a local oscillator signal.

Abstract: Multiple input and/or gain stage Gilbert cell mixer designs are disclosed. The designs allow one input to be turned on at a time, and are suitable, for example, for use in receiver and transmitter applications. In addition, the designs allow for the inputs of the multi-input Gilbert cell mixer to be connected together, thereby allowing for switching of gain states within the Gilbert cell mixer. The mixer design may include, for example, a Gilbert cell mixer stage, and a plurality of input/gain stages. Each input/gain stage has its output connected to the input of the mixer stage, and is configured for receiving an input signal and applying a gain factor to that input signal to provide a signal for mixing with the LO. Each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, so that only one input/gain stage is active at a time.

Abstract: A temperature compensated low voltage reference circuit can be realized with a reduced operating voltage overhead and reduced spatial requirements This is accomplished in several ways including integrating one or more bipolar junction transistors into a current differencing amplifier and reducing the number of components required to implement various voltage reference circuits. All of the reference circuits may be constructed with various types of transistors including DTMOS transistors.

Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Abstract: Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.

Abstract: A symmetrical, balanced, down-conversion mixer is achieved by the coordinated layout of a balanced Local Oscillator (LO) divider circuit and a balanced Radio Frequency (RF) mixer circuit, such that the LO divider is in the center and the RF mixer is arrayed symmetrically around the LO divider. In particular, the LO divider is partitioned into four portions (e.g., Ip, In, Qp, Qn), which are placed in respective quadrants, defined by orthogonal reference axes through the LO divider center. The RF mixer is similarly partitioned into four corresponding portions, which are placed around the LO divider portions in each quadrant. By integrating the LO divider and RF mixer in the layout of the symmetric, balanced, down-conversion mixer, greater component matching and control of current paths are possible, improving operational quality parameters such as IRR, IP2, and LO feedthrough.

Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.

Abstract: A Gilbert cell mixer design is disclosed. Instead of using a differential transconductance stage as typically done, the design employs a differential transimpedance amplifier input stage. By utilizing a transimpedance input stage to the Gilbert mixer, feedback is used to obtain higher linearity without sacrificing noise performance. The transimpedance input stage supplies a current signal to the cascode connected Gilbert switching quad, so the transimpedance amplifier output is taken from the collector of the transimpedance amplifier output transistor, instead of the emitter as normally done with transimpedance amplifiers.

Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.

Abstract: The present invention relates to a bidirectional frequency mixer, as well as a radiofrequency transceiver system including at least such a mixer. The mixer includes two ports separated in intermediate frequency FI, one for the reception, the other for the emission and a common port in frequency RF both for reception and for emission. It also includes at least fours mixing cells and three phase shifting means of signals used to remove the undesirable frequencies generated by the mixing cells. The mixer enables a rejection of the frequencies produced by a local oscillator in transmitting phase and a rejection of the image phase in receiving phase to be preformed. The invention is in particular applicable to designing microwave integrated circuits, in particular in millimetric frequency band.

Abstract: The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle 5 modulation to the baseband signal as additional predistortion in response to the detected envelope information. Thereby, slewing distortions in the pulse-shaped signal are removed or at least reduced.

Abstract: A mixer includes a transduction circuit, a first and a second switch circuit, and a first and a second load circuit. The transconductor circuit is for generating a differential current signal according to a differential voltage signal. The first switch circuit and the first load circuit are connected in series, and the first switch circuit is used to regulate the differential current signal in response to a first oscillator signal. The second switch circuit and a second load circuit are connected in series, and the second switch circuit is used to regulate the differential current signal in response to a second oscillator signal. The first load circuit and the second load circuit are connected at a common node to reduce harmonic interferences.

Abstract: Multiple input and/or gain stage Gilbert cell mixer designs are disclosed. The designs allow one input to be turned on at a time, and are suitable, for example, for use in receiver and transmitter applications. In addition, the designs allow for the inputs of the multi-input Gilbert cell mixer to be connected together, thereby allowing for switching of gain states within the Gilbert cell mixer. The mixer design may include, for example, a Gilbert cell mixer stage, and a plurality of input/gain stages. Each input/gain stage has its output connected to the input of the mixer stage, and is configured for receiving an input signal and applying a gain factor to that input signal to provide a signal for mixing with the LO. Each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, so that only one input/gain stage is active at a time.

Abstract: Phase noise detection systems for a device under test (DUT) are provided that can be embedded within a chip. According to one embodiment, the embedded phase noise detection system can include an active delay line cell, a phase shifter, and a phase detector. The active delay line and phase shifter separately receive the output signal of the DUT. The phase detector can include a double-balanced mixer followed by an active RC filter. The double-balanced mixer receives, as input, the outputs from the active delay line and phase shifter and can produce different dc voltages proportional to the difference from the input phase quadrature. An auto-adjustment circuit can also be included to help the input signal from the phase shifter to the mixer maintain quadrature.

Abstract: A circuit and a method for implementing frequency tripled I/Q signals are proposed, including receiving two input I/Q signals through frequency multipliers so as to generate two frequency multiplied signals and mixing the input I/Q signals and the corresponding frequency multiplied signals through mixers for generating and outputting two I/Q signals with a frequency three times that of the input I/Q signals. The invention eliminates the requirement for high amplitude of the input signals as in the prior art and has lower power consumption and broader bandwidth and can be used as high frequency signal sources in any single chip processes.

Abstract: Transmission of a high frequency signal is provided by a passive mixer. The passive mixer receives a low frequency signal as an input. The passive mixer includes a plurality of transistors each with a gate, a source, and a drain. The passive mixer also includes a local oscillator connected to the gates of the transistors. The gates of the transistors are also connected to a DC bias proportional to the threshold voltage of the transistors. In addition, an output of the passive mixer may be attenuated by a passive attenuator wherein both the passive attenuator and passive mixer are substantially free of quiescent current.

Abstract: Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: translating an inphase component of said first signal in frequency via a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and translating a corresponding quadrature component of said first signal in frequency via a phase-shifted version of said generated filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A quadrature mixer circuit and an RF communication semiconductor integrated circuit capable of suppressing variations in secondary distortion while reducing the current consumption are provided. In a quadrature mixer circuit, even if local signals different by 90 degrees inputted to the bases of I transistors and Q transistors have large amplitudes, interference is suppressed by I resistors, Q resistors, and capacitors. Also, since the capacitors are provided, changes in bias current values can be suppressed. Accordingly, variations in secondary distortion can be suppressed. Furthermore, the capacitors combine current outputs of a differential circuit formed of I transistors and the resistor and a differential circuit formed of Q transistors and the resistor. Therefore, current consumption can also be reduced.

Abstract: Methods, systems, and apparatuses, for down-converting and up-converting an electromagnetic signal. In embodiments the invention operates by receiving an EM signal and recursively operating on approximate half cycles of the carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In embodiments, up-conversion is accomplished by controlling a switch with an oscillating signal, the frequency of the oscillating signal being selected as a sub-harmonic of the desired output frequency. When the invention is being used in the frequency modulation or phase modulation implementations, the oscillating signal is modulated by an information signal before it causes the switch to gate the bias signal. The output of the switch is filtered, and the desired harmonic is output.

Abstract: A spread-spectrum signal generator includes four differential input signal terminals, a differential output signal terminal, four interconnected mixer control subcircuits, a 4-input differential mixer, a first current source having a magnitude which sets the mixer's 3 db bandwidth, and a second current source having a magnitude which controls a frequency difference between the differential output signal the differential input signals. In a preferred embodiment, this frequency difference and the frequency of the differential output signal are modulated through the modulation of the second current source magnitude. The frequency of the modulation is equal to the frequency of the second current source modulation, and the magnitude of the output signal frequency modulation is proportional to the magnitude of the second current source modulation.

Abstract: A low noise RF mixer is described. The mixer of the present invention has excellent linearity due to reduction of second-order distortion. The mixer includes an inputting stage, a switching stage and a load stage. The inputting stage includes a switching pair and a transconductance circuit. The load stage is formed by resistors. The switching stage includes a switch quad (two switch pairs). Each switch pair of the switching stage has a current source for implementation of current injection to a common source (emitter) junction of the switch pair. For each switch pair of the switching stage, an inductor is connected between the current source and the common source (emitter) junction. In addition, a capacitor is connected with the inductor.

Abstract: A circuit includes a multi-tanh cell having a common-emitter node to receive a bias current, and an extra transistor coupled to the common-emitter node to dynamically divert a portion of the bias current from the multi-tanh cell. The circuit may be arranged as a multiplier with an input network arranged to apply two or more input signals to the multi-tanh cell. A second multi-tanh cell with an extra transistor may be arranged in a feedback loop where the outputs of the first and second multi-tanh cells are coupled together at an integrating node. A buffer drives the final output and feedback cell to cancel nonlinearities in the multiplier cells.