Abstract: A microelectronic module that includes a semiconductor carrier including a FET that comprises a serpentine gate electrode having an elongated gate width and gate width-to-gate length ratio in access of 100 wherein resistive, capacitive, and inductive elements are embedded within the structure of the serpentine gate electrode.

Abstract: The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.

Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.

Abstract: A method and system for bandwidth enhancement using hybrid inductors are disclosed and may include a complementary metal oxide semiconductor (CMOS) transceiver providing an electrical impedance that increases with frequency via hybrid inductors comprising a transistor, a capacitor, an inductor, and a resistor. A first terminal of the hybrid inductors may comprise a first terminal of the transistor. A second terminal of the transistor may be coupled to a first terminal of the resistor and a first terminal of the capacitor. A second terminal of the resistor may comprise a second terminal of the hybrid inductors. A third terminal of the transistor may be coupled to a first terminal of an inductor, and a second terminal of the inductor may be coupled to a second terminal of the capacitor. The hybrid inductors may be configured by varying transconductance, resistance, and/or capacitance and may be utilized as an amplifier load.

Abstract: A method and system for bandwidth enhancement using hybrid inductors are disclosed and may include providing an electrical impedance that increases with frequency via hybrid inductors comprising a transistor, a capacitor, an inductor, and a resistor. A first terminal of the hybrid inductors may comprise a first terminal of the transistor. A second terminal of the transistor may be coupled to a first terminal of the resistor and a first terminal of the capacitor. A second terminal of the resistor may comprise a second terminal of the hybrid inductors. A third terminal of the transistor may be coupled to a first terminal of an inductor, and a second terminal of the inductor may be coupled to a second terminal of the capacitor. The hybrid inductors may be configured by varying transconductance, resistance, and/or capacitance and may be utilized as an amplifier load.

Abstract: A driver circuit for a high frequency switching circuit such as a converter for a gas discharge lamp includes a resonant circuit which transfers energy from the parasitic input capacitance of one or more power switching devices during switching of the latter. The energy transfer prevents dissipation of the capacative energy in the driver circuit which may otherwise destroy one or more components of the driver circuit. The resonant circuit includes a discrete inductor in the driver circuit. Preferably, one or more discrete capacitors are also included within the driver circuit to maintain resonance at a given frequency regardless parasitic capacitance variation.

Abstract: P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed in the P type well regions 31 and 32 respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Abstract: A transconductance cell has first and second transistors, each transistor having a control terminal and first and second terminals. A signal is output from the second transistor in response to a voltage input applied to the control terminal of the first transistor. The transconductance cell includes a linear element coupled between the first terminal of the first transistor and the first terminal of the second transistor. A tank circuit is coupled between a reference potential and a node between the linear element and the first terminal of the second transistor.

Abstract: There is disclosed a bifrequency output device. The bifrequency output device comprises Josephson junctions, a resistor for generating a given voltage in response to a pulse current which is supplied from the outside, and a time delay element for delaying the voltage generated by the resistor during a given time period and then providing it to the superconducting elements, so that the bifrequency output device outputs different low frequency and low voltage and high frequency and high voltage depending on the initial condition of the superconducting elements constituting the Josephson junctions and the voltage with a given delay time which is induced to the superconducting elements.

Abstract: In a motor controller circuit, an integrated circuit driver drives a plurality of switching transistors which are organized along a top rail and a bottom rail. To reduce the conduction of current through the parasitic diode D.sub.S1 of the integrated circuit, the switching transistors at the bottom rail are provided with individual Kelvin emitter connections, which reduce the parasitic internal inductances, which otherwise produce highly negative voltages when the top rail transistors are turned off. Further, individual traces are provided on the printed circuit board from the COM terminal to the Kelvin emitters. Finally, a small resistance is provided in series with each Kelvin emitter connection which increases the resistance in series with the parasitic diodes and hence reduces the current flowing in the parasitic diodes.

Abstract: A protected switch has a power first semiconductor device having a first main electrode for coupling to a first voltage supply line, a second main electrode coupled to a first terminal for connection via a load to a second voltage supply line and an insulated gate electrode coupled to a control terminal for supplying a gate control signal to enable conduction of the power semiconductor device. A control arrangement has a normally off second semiconductor device having first and second main electrodes coupling the normally off semiconductor device between the gate electrode of the power semiconductor device and one of the first and second main electrodes of the power first semiconductor device and a control electrode coupled via a resistance to the gate electrode of the power semiconductor device thereby causing the normally off semiconductor device to be rendered conducting when a gate control signal is supplied to the gate electyrode to enable conduction of the power semiconductor device.