Abstract: The present disclosure provides a gate circuit and a gate drive circuit for a power semiconductor switch, including: a zener diode and a charge dissipation circuit. A first end of the zener diode is connected to a first end of the charge dissipation circuit and a gate of the power semiconductor switch, a second end of the zener diode is connected to a second end of the charge dissipation circuit and a second end of the power semiconductor switch. A first parasitic capacitor is formed between a first end and the gate of the power semiconductor switch, and a second parasitic capacitor is formed between the gate and the second end of the power semiconductor switch.

Abstract: A gate driver of a power device includes an inductor and a supply. The inductor is configured to, during a transitional period of the power device, convert a potential on a gate to a field, and the field to an opposite potential to toggle the gate and charge a floating capacitor to the opposite potential as an excess field collapses. The supply is configured to maintain the gate at the potential and generate the excess field during a non-transitional period.

Abstract: The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.

Abstract: A circuit for automatically compensating beta variation by driving base of BJT with JFET is disclosed. The circuit includes a first well, a second well, a third well, one or more leakage current devices, and a varying metal connection. The first well includes first JFET J1, second JFET J2, third JFET J3 and fourth JFET J4. The input voltage value is combination of emitter to base voltage of first BJT Q1, emitter to base voltage of second BJT Q2. The second well includes first BJT Q1, second BJT Q2 and second diode D2. The third well includes first diode snubber D1. The one or more leakage current devices are connected between base of Q1 and base Q2 to remove excess leakage current across the second well. The varying metal connection is connected across the first well, the second well and the third well to obtain beta value.

Abstract: In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit. Also included can be a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit and generates a level-shifted set signal or reset signal; and a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit.

Abstract: A basic and simple power control circuit for selectively controlling power to an electronic device is provided. The electronic device includes a power module, a system power port, and a processing unit, the processing unit includes a first and a second power control pins. The power control circuit includes a power switch, a trigger signal producing sub-circuit, a trigger-receiving sub-circuit, and a switch controlling sub-circuit. The switch is connected between the power module and the system power port. The trigger signal producing sub-circuit produces a trigger signal. When receiving a trigger signal, the trigger-receiving sub-circuit follows a first control signal output by the second power control pin to output the first control signal. The switch controlling sub-circuit turns off the power switch when receiving the first control signal.

Abstract: Disclosed is a control circuit for control of a semiconductor switching device, such as an IGBT. The control circuit comprising a first feedback path between a first electrode and a control electrode of said semiconductor switching device which has a capacitance. The circuit is operable such that the capacitance in the first feedback path is dependent on the voltage level at said first electrode. In another embodiment the control circuit is operable such that a feedback signal begins to flow in the first feedback path immediately as the semiconductor switching device begins switching off, thereby causing a control action on the semiconductor switching device.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: In a gate drive circuit, a gate voltage limiting circuit limits a gate voltage equal to or lower than a first limiting voltage in a first period, and limits the gate voltage equal to or lower than a second limiting voltage in a second period. A gate voltage generation circuit generates a drive voltage having a first set value, which is determined to operate the transistor in an active region, in the first period, and generates the drive voltage having a second set value, which is determined based on a gate withstand voltage of the transistor and loss in an on operation of the transistor in a saturated region, in the second period. The first limiting voltage is higher than the first set value by a predetermined value. The second limiting voltage is higher than the second set value by a predetermined value.

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract: According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor.

Abstract: A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

Abstract: A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: A gate driving circuit for driving a power semiconductor element can include a MSINK that is an n-channel metal-oxide silicon field-effect transistor (MOSFET) with a low resistance value for rapidly drawing out the charges accumulated on the gate of an insulated gate bipolar transistor (IGBT), and a MSOFT that is an n-channel MOSFET with a high resistance value for slowly drawing out the charges. By shifting the time for turning ON of these MOSFETs, soft interruption can be performed rapidly and surely when overcurrent or short circuit current flows in the IGBT. Therefore, device breakdown is minimized or avoided and noise generation is suppressed.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes a discharge circuit and a control circuit. The discharge circuit includes a first transistor connected between a gate of an output transistor and an output terminal, and a capacitor connected to a gate of the first transistor, and discharges a gate voltage of the output transistor to the output terminal by turning on the first transistor with an electric charge of the capacitor. The control circuit includes a charge path, a first discharge path, and a second discharge path. The first discharge path discharges an electric charge of the charged capacitor when the system turns off. The second discharge path discharges the electric charge of the capacitor for a time period longer than a time period for discharging the output transistor by the discharge circuit upon detection of an abnormality in the system.

Abstract: A solid state relay has independent charge pumps isolating each gate of a full bridge to achieve faster and proper gate turn on. The low side MOSFETs of the bridge are the current sensing device reducing loss and allowing a device controlled by the relay to achieve peak performance. Dynamic braking is achieved by the two low side MOSFETs being fully conducted and applying a load across the DC motor. Addition of a microprocessor to the device provides undervoltage sensing, current vs time readings, motor stall sensing, and motor temperature sensing. Motor temperature is detected by checking impedance of the motor at microsecond pulses to see if the motor is getting hot.

Abstract: An electrically noisy D.C. power source having high slew rate A.C. transient voltage, is cut off from a capacitive load by a switchable, constant slew rate voltage source, upon the detection of an A.C. transient voltage having a slew rate that would otherwise cause a current overload through the capacitive load or the voltage source, or the D.C. power source.

Abstract: A subject of the present invention is to reduce noise caused by ringing or the like while reducing turn-on power loss of the element and reverse recovery loss of the diode in a switching circuit of a power semiconductor element to which a SiC diode having small recovery current is connected in parallel. A means for solving the problem is to detect gate voltage and/or collector voltage of the power semiconductor switching element and change gate drive voltage in several stages based on the detected value.

Abstract: The invention concerns a method for controlling a switching assembly comprising a plurality of transistors connected in parallel, having a linear operating mode, a closed-switch operating mode and an off operating mode including a first operating phase during which a current flows from a source terminal to a drain terminal and a second operating phase during which no current flows. The method includes the following successive steps; (a) controlling the switching assembly in closed-switch mode during part of the first phase; (b) controlling the switching assembly in linear mode; (c) controlling the assembly in off mode during part of the second phase.

Abstract: Methods, systems and apparatus for a controller for fast transient response, the controller including a linear compensation circuit for controlling output voltage during steady state operation and a non-linear control circuit to generate a non-linear signal during transient periods, only a first pulse of the non-linear signal is injected during each transient period. The combination linear and non-linear control provides stability and reduces delay times for fast transient response. The non-linear control circuit includes a step up and a step down non-linear control circuit for producing the non-linear signal with a short delay time when the load voltage is less or greater than the reference voltage. An embodiment includes an adaptive circuit or generating a current signal dependent on the load current, the current signal is combined with the output voltage to reduce the difference between the reference and output voltages.

Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.

Abstract: An overcurrent protection circuit for a power switching transistor wherein the power switching transistor has a control electrode and two main electrodes, the circuit comprising a circuit including a protection switch for sensing the rate of change of voltage with respect to time at one of the main electrodes of the power switching transistor and for controlling the protection switch to remove a control signal to the control electrode of the power switching transistor to turn off the power switching transistor if the rate of change exceeds a predefined value.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: A gate drive circuit for driving the gate of a power transistor switch comprising a gate drive sourcing circuit supplying gate drive current to the power transistor switch, the gate drive sourcing circuit initially providing a first current to the gate of the power transistor switch and then providing a second current to the gate of the power transistor switch; a circuit for driving the gate drive sourcing circuit, the circuit having a first input for driving the gate drive sourcing circuit to turn on the power transistor switch by providing the first current, the circuit further having a second input coupled to a voltage across the power transistor switch and being controlled by the second input to cause the gate drive sourcing circuit to provide the second current when the voltage across the power transistor switch begins to drop as the power transistor switch begins to turn on.

Abstract: Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.

Abstract: A system and method is provided for driving a power field-effect transistor (FET). In one embodiment, a system comprises a control circuit that generates a control signal to provide a gate voltage of the power FET. The system further comprises a slope control circuit coupled between the control circuit and the power FET that is operative to dynamically control the rate-of-change of a gate voltage of the power FET to reduce electromagnetic interference (EMI) emissions and power loss resulting from switching the power FET.

Abstract: A protection circuit monitors the gate voltage of an insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) to protect the transistor during a time when it is being turned on. In one embodiment, the circuit monitors a transient gate voltage of the transistor when it is turned on. A short or overcurrent condition is detected when the gate voltage exceeds a delayed reference signal.

Abstract: A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.

Abstract: A switching circuit of the present invention can be advantageously used in an electronic control unit mounted on an automotive vehicle. The switching circuit is constituted by a pair of P-channel MOS-FETs connected in series between an input terminal and an output terminal. Sources of both MOS-FETs are connected to a common source junction and gates thereof are connected to a common gate junction. A Zener diode connected between the common source junction and the common gate junction is used for protecting the MOS-FETs. A resistor is connected in parallel to the Zener diode to bring the switching circuit to a non-conductive state when the gate voltage at the common gate junction becomes indefinite and a high voltage is supplied to the output terminal. In place of the resistor, an additional P-channel MOS-FET may be used in the switching circuit to bring the switching circuit to the non-conductive state when the voltage at the common gate junction becomes indefinite.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS): correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors: capacitors (C2, C3) connected between the control terminals and the input terminal: diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a system controller. Power switches in both a power converter and power inverter are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller. The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive. A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction.

Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.

Abstract: The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affects a slew rate.

Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.

Abstract: A gate driver for a power switch, comprising a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch; a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; and a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch.

Abstract: As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means (2) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means (1).

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

Abstract: A high frequency switching device includes a control terminal, a power source terminal, a GND terminal, an RF terminal, a switch section, a control section, and protecting diodes. The switch section switches input/output routes of an RF signal input from the RF terminal. The control section controls the switching section, and is connected to the control terminal and the power source terminal. The protecting diodes are provided between the control terminal and the RF terminal, between the control terminal and the GND terminal, and between the power source terminal and the GND terminal.

Abstract: The invention relates to a comprehensive control method for switch on and off processes of power semiconductor switches (S1–S4). In a switching phase A the collector current transient dic/dt is controlled in order to safeguard a controlled clear-off of the edge zones of a serial freewheeling diode (Ds). In a switching phase B the collector voltage gradient dvCE/dt is controlled in order to specifically switch the power semiconductor switch (S1–S4), thereby establishing a closed control loop by returning primary and optionally secondary condition variables (vc, dvc/dt, ic, dic/dt, iG, vG, diG/dt, dvG/dt) of the power semiconductor switch (S1–S4).

Abstract: A drive circuit for a power semiconductor device includes: a sampling signal generating circuit for detecting that an input control signal instructs OFF and outputting a sampling signal at the time instant of start of a Miller period of time of an IGBT; a gate voltage detecting circuit for detecting a Miller voltage of the IGBT at the timing when the sampling signal is inputted and outputting, when the Miller voltage is equal to or larger than a threshold, an over-current detection signal; and a gate voltage controlling circuit for controlling, in response to the over-current detection signal, a gate voltage of the IGBT in such a way that the IGBT is turned OFF at slower speed than in the normal state. Thus, it is possible to suppress a surge voltage which is generated when the IGBT is turned OFF during the flow of an over-current.

Abstract: A method and structure for providing dynamic control of a slew rate of an electronic circuit. The structure has a signal line that is coupled to a number of capacitive elements that may be selectively switched in or out of the electronic circuit in order to provide precise control of the slew rate of the electronic circuit. A control element switches the capacitive elements into the signal line so that the slew rate may be precisely controlled at one or more time instants. The method includes determining a desired slew rate of the electronic circuit. Based upon the desired value of the slew rate, one or more of the capacitive elements are switched into the signal line at one or more time instants without changing an output impedance of the electronic circuit.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d