Abstract: A bidirectional switch fault protection circuit includes a bidirectional switch circuit, a desaturation detection circuit, and a gate driver. The bidirectional switch circuit generates first and second switch voltages based on a direction of electric current. The desaturation detection circuit outputs the first switch voltage in response to the electric current flowing in a first direction and outputs the second switch voltage in response to the electric current flowing in a second direction opposite the first direction. The gate driver receives the first switch voltage in response to the electric current flowing in the first direction and the second switch voltage in response to the electric current flowing in the second direction. The gate driver detects a first short circuit condition based on the first switch voltage and a second short circuit condition based on the second switch voltage.

Abstract: A radio frequency device and a voltage generating device thereof are provided. The voltage generating device includes a first transistor, a second transistor, and a voltage dividing circuit. A first terminal of the first transistor receives a first voltage. A first terminal of the second transistor receives a second voltage. A first connection terminal and a second connection terminal of the voltage dividing circuit are respectively coupled to second terminals of the first transistor and the second transistor. The voltage dividing circuit generates a first divided voltage and a second divided voltage. The first divided voltage is used as an output voltage of the voltage generating device. The second divided voltage is output as a control voltage to a control terminal of the first transistor and a control terminal of the second transistor.

Abstract: A radio frequency apparatus and a voltage generating device thereof are provided. The voltage generating device includes a first switch and a second switch. A first terminal of the first switch receives a first voltage. A control terminal of the first switch receives a second voltage. A first terminal of the second switch receives the second voltage. A control terminal of the second switch receives the first voltage. A second terminal of the second switch and a second terminal of the first switch are coupled to an output node, wherein the output node outputs an output voltage related to at least one of the first voltage and the second voltage.

Abstract: A solid state circuit includes a main and a floating circuit including: a first driver for generating a differential driver signal derived from a driver signal; a modulator configured for modulating a modulator signal with another signal to obtain a differential control signal; the floating circuit comprising: a floating power supply comprising at least one rectifier configured for generating a floating supply voltage (VDDF) and a floating ground voltage (VSSF) from the differential driver signal; a demodulator configured for demodulating the differential control signal and for passing the demodulated signal to an output switch; the output switch comprising a first output node and a second output node and at least one transistor configured for opening or closing an electrical path under control of the demodulated signal.

Abstract: A transistor switching circuit and an integrated circuit thereof are provided. The transistor switching circuit includes: at least two transistors M1 and M2, and a voltage follower. The gate of the transistor M1 and the gate of the transistor M2 are connected to a first node G, the first node G is connected to a first current source, and the source of the transistor M1 and the source of the transistor M2 are connected to a second node S1. The voltage follower includes a transistor M3 and a second current source. The gate of the transistor M3 is connected to the second node S1, and the source of the transistor M3 is connected to the second current source. One end of a resistive device is connected to the source of the transistor M3, and another end of the resistive device is connected to the first node G.

Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.

Abstract: In an aspect, a circuit can include drain and source terminals; a HEMT having a drain and a source, wherein the drain is coupled to the drain terminal; and a variable resistor having a first electrode and a second electrode. The first electrode can be coupled to the source of the HEMT, and the second electrode can be coupled to the source terminal. In another aspect, an electronic device can include a source terminal; a heterojunction between a channel layer and a barrier layer; a source electrode of a HEMT overlying the channel layer; a first resistor electrode overlying the channel layer and spaced apart from the source electrode, wherein the first resistor electrode is coupled to the source terminal; and a variable resistor, wherein from a top view, the variable resistor is disposed along the heterojunction between the source electrode and the first resistor electrode.

Abstract: In described examples of a circuit that operates as a low-power ideal diode, and an IC chip that contains the ideal diode circuit, the circuit includes: a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal; a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor; and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage.

Abstract: A switching element driving circuit that includes a push-pull buffer circuit driving a switching element to be driven, the push-pull buffer circuit amplifying electrical power of a switching control signal and transmitting the amplified switching control signal to a control terminal of the switching element to be driven; a compensation resistor that connects the input to the output; and an input-side pull-down resistor that connects the input to a negative polarity side of the switching element to be driven.

Abstract: Systems, circuits, and chips for protecting transistors and circuits containing transistors are provided. As an example, a transistor (e.g., an Insulated-Gate Bipolar Transistor (IGBT)) monitoring system is disclosed to include an IGBT desaturation detection circuit that is configured to check and monitor desaturation functionality of the IGBT before startup of the IGBT as well as during operation of the IGBT.

Abstract: A digital active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction is presented. The circuit contains switching means comprising an array of switches, a first comparison unit coupled to the digital active diode circuit input and output. The first comparison unit updates its output if the difference between their inputs is higher than a first threshold voltage, and a second comparison unit being coupled to the digital active diode circuit output and input. The second comparison unit updates its output if the difference between its inputs is lower than a second threshold voltage. The switching means switches on or off at least one switch based on the comparisons performed by the first comparison unit and the second comparison unit and wherein the first threshold voltage is different from the second threshold voltage.

Abstract: Systems and methods are disclosed, including, for example, a low-voltage control circuit configured to receive a charge pump voltage, a rail voltage, and a switch control signal, to provide the charge pump voltage when the switch control signal is in a first state, and to provide the higher of the charge pump voltage and the rail voltage when the switch control signal is in a second state. The system can include a first pick-high circuit configured to receive the rail voltage and the charge pump voltage, and to provide the higher of the rail voltage and the charge pump voltage at an output. The switch control signal, in the first state, can include the output of the pick-high circuit. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.

Abstract: In some examples, an ink level sensor includes a sense capacitor between a first node and ground, a first switch to couple a first voltage to the first node and charge the sense capacitor, a second switch to couple the first node with a second node and share the charge between the sense capacitor and a reference capacitor, causing a second voltage at the second node, and a transistor having a drain, a gate coupled to the second node, and a source coupled to ground, the transistor to provide a drain to source resistance in proportion to the second voltage.

Abstract: A gate voltage control device includes a detection circuit, a plurality of isolation transformers including primary coils and secondary coils, a primary circuit connected to the primary coils, secondary circuits connected to the secondary coils, and voltage regulator circuits connected to the secondary circuits and gates. The detection circuit transmits signal corresponding to detected physical quantity to the primary circuit. The primary circuit cyclically performs applying a variable voltage in a waveform that corresponds to the signal transmitted from the detection circuit between both ends of each primary coil. Each secondary circuit converts the variable voltage generated in the corresponding secondary coil to a direct voltage.

Abstract: A bidirectional MOSFET switch is provided. The switch includes an input terminal, an output terminal and two MOSFET transistors which are connected to one another by their source and gate terminals. The input and the output terminals are connected to a respective drain terminal of the two MOSFET transistors. The switch further includes a control input terminal that is galvanically isolated by a potential isolator and connected to a control unit configured to switch a control current for a FET transistor via a further MOSFET transistor. The FET transistor is configured to generate, by the control current, a gate voltage Vgs between the gate and the source at the two MOSFET transistors for the switching thereof, and a floating voltage source, which is galvanically connected to the input and which is configured to generate a gate control current for the two MOSFET transistors.

Abstract: An apparatus includes a first set of circuits adapted to operate in a first mode of operation of the apparatus. The apparatus further includes a second set of circuits adapted to operate in a second mode of operation of the apparatus, where a power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. The apparatus also includes a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, and the second supply voltage powers the second set of circuits.

Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

Abstract: A compensation circuit includes an amplifier coupled between a first voltage terminal and a common terminal. The amplifier has a first output terminal. A current source transistor has a current path coupled between a second voltage terminal and a second output terminal. A threshold voltage sense transistor has a current path coupled between the first and second output terminals. A gate and drain of the threshold voltage sense transistor are connected. An output transistor having a current path coupled between the first output terminal and a third output terminal has a gate coupled to the second output terminal.

Abstract: In an embodiment, semiconductor switch includes first switches switching conduction between input-output nodes and a common node. One of the first switches includes a plurality of first transistors connected in series between an input and output node and the common node. Each of the plurality of first transistors includes first gate electrodes, a second gate electrode, a first and second region in a semiconductor layer having a same conduction type. The first gate electrodes extend in parallel in a first direction. The second gate electrode extending in a direction crossing the first direction and is connected to one end of the first gate electrodes. The second region in the semiconductor layer is disposed on a side of the second gate electrode opposite to the first gate electrodes.

Abstract: Disclosed is an output buffer. The output buffer includes a first amplifier configured to amplify an input signal, and output first to fourth amplified signals according to results of the amplification, a first transistor to receive the first amplified signal, a second transistor to receive the second amplified signal, a third transistor to receive the third amplified signal, a fourth transistor to receive the fourth amplified signal, a first node, connected to drains of the first and second transistors, a second node, connected to drains of the third and fourth transistors, an output node connected to the first and second nodes, and a first controller configured to selectively supply a control voltage to the gates of the first to fourth transistors in response to a control signal.

Abstract: A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

Abstract: Systems, methods, and devices to control a transistor to maintain one or more substantially constant characteristics while activated or deactivated are provided. One such system includes a transistor that receives an activation signal on a gate terminal to become activated during a first period and receives a deactivation signal on the gate terminal to become deactivated during a second period. The transistor receives an input signal on an input terminal during the first period and the second period. The input signal varies during the first period and during the second period. The transistor may have improved reliability (e.g., substantially constant on resistance RON) because a first difference between the input signal and the activation signal substantially does not vary during the first period and a second difference between the input signal and the deactivation signal substantially does not vary during the second period.

Abstract: In order to increase the switching speed of an RF FET in an RF shunt circuit, a second, smaller, FET, with respect to the size of the RF FET, is connected directly to the gate of the RF FET to shunt the gate to ground quickly when switched from the off-state to the on-state. The smaller FET switches faster, due to being smaller than the larger RF FET, but it is effectively open-circuited in terms of RF performance when off because it is so small.

Abstract: A receiving circuit with an ultra-wide common-mode input voltage range applies to a controller area network (CAN) and comprises a resistor assembly electrically connected with a CANH and a CANL, a reference amplifier, a first input amplifier assembly, a second input amplifier assembly, and an analog adder. The receiving circuit receives voltages from the CANH and CANL. The resistor assembly bucks voltage, respectively generating CANH and CANL voltage divisions at first and second nodes and outputting the voltage divisions to the first and second input amplifier assemblies. The first and second input amplifier assemblies amplify the differential signal between the first and second nodes and convert the differential signal into single-end signals. The analog adder adds the single-end signals as the output signal. The receiving circuit can receive the signal ranging between the maximum and minimum common-mode voltages and reduce electromagnetic emission.

Abstract: A high voltage analog switch can be used in medical ultrasound applications. The high voltage analog switch can pass high voltage transducer excitation signals without necessarily having any high voltage power supplies. The high voltage analog switch can include three output switches, with one of the output switches having a clamp circuit for ensuring that transistors of an output switch on an input end of the high voltage analog switch remain OFF when the high voltage analog switch is OFF.

Abstract: Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance.

Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.

Abstract: A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction.

Abstract: An auxiliary voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The auxiliary voltage may be a bias voltage and/or a voltage used to power an inverter used to enable a selected branch as an isolation branch or shunt branch.

Abstract: A desaturation detection circuit for use between the desaturation detection input of an optocoupler and the output of a power switching device, the desaturation detection circuit comprising: a threshold setting element having an input and an output, the input for connection to the output of a power switching device via one or more diode(s), the threshold setting element being arranged to set a threshold voltage at the input at which the threshold setting element will provide an output at the output of the threshold setting element when the input voltage is exceeded, and a detector having an input connected to the output of the threshold setting element and an output connectable to a desaturation detection input of an optocoupler, the detector being arranged to detect an output at the output of the threshold setting element and in response to provide a control signal at the output of the detector for the desaturation detection input to trigger a desaturation routine in the optocoupler.

Abstract: A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.

Abstract: An LED driver circuit is provided with protection against short circuits between output terminals. Two switches are coupled in series with the LED load. A first capacitor is coupled to gate terminals for the first and second switches and defines a first gate charge time. A first failure detection circuit includes a third switch coupled across the first capacitor, a second capacitor defining a second gate charge time for the third switch, the second gate charge time being less than the first, and a zener diode having a threshold voltage less than a maximum output voltage during normal operation. The failure detection circuit disables the third switch during normal operation, and during short conditions enables the third switch to short the gates of the first and second switches. A second failure detection circuit is identical to the first, and coupled in parallel to protect against circuit failure.

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.

Abstract: A gate driver that drives a field-effect transistor on the basis of an input signal includes a comparator that compares an applied voltage applied between the drain and the source of a field-effect transistor to a reference voltage for detecting noise occurring between the drain and the source of the field-effect transistor, and a gate voltage switching circuit that, if the field-effect transistor is off, switches the voltage applied between the gate and the source of the field-effect transistor from a first voltage to a second voltage when the output of the comparator transitions from a state indicating that the applied voltage between the drain and the source is less than the reference voltage to a state indicating that the applied voltage between the drain and the source is equal to or greater than the reference voltage.

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.

Abstract: A Radio Frequency (RF) switch element is described. The RF switch element comprises a primary transistor element for facilitating switching an RF signal between circuit nodes. A pair of secondary transistor elements are also provided. The pair of secondary transistor elements are co-operable with the primary transistor element and provide respective signal paths which have a lower impedance level than an intrinsic element associated with the primary transistor element.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: A boost converter for driving the gate of n-channel MOSFET power devices is described. The boost converter includes a monitoring circuit and a kick start circuit to quickly bring the boost converter online when required to drive the MOSFET on.

Abstract: In a driver, a charging module electrically charges the on-off control terminal of the switching element for turning on the switching element, and a limiting module performs a task of limiting a voltage at the on-off control terminal of the switching element by a predetermined voltage to thereby limit an increase of a current flowing between the input and output terminals of the switching element. A determining module determines whether the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage while the limiting module is performing the limiting task. A correcting module corrects the voltage at the on-off control terminal of the switching element to be close to the predetermined voltage when it is determined that the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage.

Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: A method and corresponding circuits for operating a parallel DMOS switch that includes a pair of P-type DMOS devices connected in series with each other and in parallel with a pair of N-type DMOS devices connected in series with each other. The method and circuits involve turning the switch on by applying gate signals to the DMOS device pairs which are generated using at least one source voltage of a DMOS device pair. The switch is turned off by setting the gate signals equal to the respective source voltages of the DMOS device pairs.

Abstract: A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.