Abstract: An output buffer includes a first group of stagger FETs coupled in parallel between a power lead and an output signal lead and a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead. Each stagger FET has a gate coupled to a respective base resistor and a respective adjustable resistor. A first group of bypass FETs and a second group of bypass FETs are each coupled across the terminals of a respective adjustable resistor and the gates of the bypass FETs are coupled to either a first process-sensing signal lead or a second process-sensing signal lead.

Abstract: A dynamic bias current generator includes a detection circuit and at least one current generating circuit. The detection circuit is used for generating a detection signal, and includes: current source coupled to the power supply voltage; a first set of transistors coupled between the current source and the ground voltage; a second set of transistors coupled between the power supply voltage and the ground voltage; a first capacitor coupled to the power supply voltage; and a second capacitor coupled to the ground voltage. The at least one current generating circuit is used for generating dynamic bias current according to the detection signal, and includes multiple transistors and a terminal for outputting voltage signal corresponding the dynamic bias current. The dynamic bias current may be used to increase the reaction speed of the comparator and may be used in a power down detection circuit.

Abstract: The present disclosure illustrates a low-power voltage detection circuit, including a threshold voltage detection circuit, a leakage detection circuit and a low-voltage detection circuit. By utilizing the above-mentioned threshold voltage detection circuit and leakage detection circuit, the voltage variations caused by leakage, temperature or process can be detected in the more efficient and power saving way.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

Abstract: Disclosed is an apparatus and method for controlling switching devices for a DC motor, which controls the dead-time in an on-chip manner, even when a microcontroller is not mounted in a vehicle controller, by providing a semiconductor chip for controlling switching devices for a DC motor. More specifically, switching devices are mounted in a semiconductor chip to configure an internal circuit of the chip with a half-bridge and a dead-time controller is provided on the semiconductor chip and is configured to transmit gating signals by controlling dead-time periods during operation of the switching devices and drive the switching devices directly connected to a motor.

Abstract: An apparatus includes a switch module, a sense circuit coupled to the switch module and configured to indicate an operating conduction mode of the switch module, and a drive circuit operatively coupled to the switch module to enable and disable forward conducting mode of the switch module. Once the switch module is in forward conducting mode, the drive circuit is configured to maintain enablement of the forward conducting mode even if the sense circuit indicates reverse conduction mode.

Abstract: Provided is a power converter having a switching circuit wherein a surge voltage of a plurality of switching elements connected in series is suppressed and loss is not concentrated to a specific switching element. The switching circuit is provided with: a non-latching type switching element having two main terminals and one control terminal; a voltage detecting means which detects a voltage applied between the main terminals of the switching element; a control current supply for supplying the control terminal with a control signal corresponding to the voltage detected by the voltage detector; and a delay device for delaying the control signal.

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Abstract: A slew rate enhancing system includes first and second modules. The first module is configured to generate a first output signal in response to complementary first and second input signals. The second module is configured to generate a second output signal in response to the first and second input signals. The first module is configured to switch between tracking the first input signal and not tracking the first input signal during each half cycle of the first input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the first module. The second module is configured to switch between tracking the first input signal and not tracking the second input signal during each half-cycle of the second input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the second module.

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal.

Abstract: Capacity degradation due to charge/discharge cycles is suppressed in either a non-aqueous electrolyte secondary cell provided with a positive electrode including, as a positive electrode active material, a lithium-transition metal complex oxide having a layered structure and containing at least Ni and Mn as transition metals, and a negative electrode containing a carbon material as a negative electrode active material and having a higher initial charge-discharge efficiency than that of the positive electrode, or an assembled battery having a plurality of cells each of which is the secondary cell. A control circuit incorporated in the secondary cell or the assembled battery, or in an apparatus using the secondary cell or the assembled battery, monitors the voltage of the secondary cell or each of the cells in the assembled battery so that the end-of-discharge voltage of each cell is 2.9 V or higher.

Abstract: Methods and apparatus for regulating a synchronous rectifier DC-to-DC converter by adjusting one or more existing synchronous rectifiers in the converter are provided. By regulating an existing synchronous rectifier, the rectifier may function as a modulator for post regulation over a limited range of output voltages suitable for load regulation, without introducing an additional conversion stage for post regulation, which typically decreases efficiency and power density. Independent post regulation of an existing synchronous rectifier may improve the load regulation, reduce output voltage ripple and improve the transient response of the converter. By operating independently from the main control loop, post regulation may most likely avoid the limitations of the main control loop, such as limited gain bandwidth and a relatively slow transient response. Such post regulation may be added to isolated or non-isolated switched-mode power supplies, such as forward or buck converters.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A semiconductor device has multiple high-side field-effect transistors and multiple low-side field-effect transistors connected to a single output terminal to generate an output signal. A driver circuit outputs driving signals that turn the field-effect transistors on and off. The driving signal for the field-effect transistors on each side is conducted by a salicided gate line with salicide block areas that produce successive delays, causing the field-effect transistors to turn on sequentially. Alternatively, the transistors have different threshold voltages, or the driving signals for different transistors are output from drivers with different driving abilities, again causing the transistors to turn on sequentially. The output signal therefore rises and falls gradually, reducing electromagnetic interference.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: Methods and apparatus for regulating a synchronous rectifier DC-to-DC converter by adjusting one or more existing synchronous rectifiers in the converter are provided. By regulating an existing synchronous rectifier, the rectifier may function as a modulator for post regulation over a limited range of output voltages suitable for load regulation, without introducing an additional conversion stage for post regulation, which typically decreases efficiency and power density. Independent post regulation of an existing synchronous rectifier may improve the load regulation, reduce output voltage ripple, and improve the transient response of the converter. By operating independently from the main control loop, post regulation may most likely avoid the limitations of the main control loop, such as limited gain bandwidth and a relatively slow transient response. Such post regulation may be added to isolated or non-isolated switched-mode power supplies, such as forward or buck converters.

Abstract: In a particular embodiment, an apparatus includes a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.

Abstract: A method for processing a signal includes monitoring an over-sampled signal to detect deviations in a number of fill samples, and providing an electronic delay adjustment to a signal path. If a deviation in the number of fill samples is detected, the electronic delay adjustment from the signal path is removed in one or more steps until all of the electronic delay adjustment is removed from the signal path.

Abstract: An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A method for operating a current limit power switch for supplying power to a load include activating the power switch to start supplying power to the load; limiting the current drawn by the power switch to a first current limit for a first, fixed duration; after the first, fixed duration, limiting the current drawn by the power switch to a second current limit for a second duration where the second current limit is less than the first current limit; and after the second duration, limiting the current drawn by the power switch to a third current limit where the third current limit is less than the second current limit.

Abstract: A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing procedure utilizes enabling one of a plurality of independent programmable current sources and a flip-flop to toggle in response to the enabled current source to indicate a physical connection of the enabled distributed logic circuit current source.

Abstract: A phase adjusting circuit is provided that is capable of adjusting a delay time at a rise or fall of a driving signal for driving an inverter. A phase adjusting circuit is provided upstream of a driver circuit, and an output from a hysteresis comparator is input to the driver circuit through the phase adjusting circuit. The phase adjusting circuit delays at least either rise or fall of the signal input to the driver circuit to adjust any difference between the pulse width of the input signal input to the driver circuit and the pulse width of a signal output from a switching element of an inverter driven by the driver circuit.

Abstract: A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.

Abstract: An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

Abstract: A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inactivation of the first signal and the activation of the second signal may be different than the delay between the inactivation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected.

Abstract: The voltage comparator of the present invention comprises a sense amplifier connected to a latch. The sense amplifier has a first input terminal for connecting to the input voltage under consideration and a second input terminal for connecting to the reference voltage. The sense amplifier generates two voltages of opposite logic values (i.e., high or low). A latch accepts these two voltages and generates an output voltage that is indicative of whether the voltage under consideration is higher or lower than the reference voltage. In another embodiment, a signal conditioning circuit is used to reduce the transients in the input voltage under consideration and perform level shifting function.

Abstract: A TTL controller system includes at least one timer system that generates a timing signal and at least one trigger system coupled to the at least one timer system and to each of the devices. The trigger system in response to the timing signal triggers with a trigger signal at least one operation in at least one of the devices. A time period for executing the at least one operation in at least one of the devices is adjustable.

Abstract: A delay locked loop having an adjustable capacitance stage is provided. The adjustable capacitance stage facilitates a selective post-silicon adjustment of capacitance amounts between a DLL loop filter capacitance and a power supply noise filter capacitance, thereby allowing a designer to reduce capacitance area space wastage and to obtain an optimal DLL performance level.

Abstract: A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

Abstract: An adjustable output voltage power converter. The power converter has a positive voltage output terminal, a negative voltage output terminal, a voltage comparator, a voltage shift resistor and a current source. The voltage comparator has a first input terminal, a second input terminal and a compare output terminal. The second input terminal picks up a reference voltage. The compare output terminal is electrically connected to one terminal of a Zf. The first input terminal is electrically connected to a second terminal of the Zf and one terminal of a Zi. The other terminal of the Zi is electrically connected to the current source and one terminal of the voltage shift resistor. The other terminal of the voltage shift resistor is electrically connected to the positive voltage output terminal.

Abstract: A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trailing edge of a control input signal, which is detected by the edge detection circuit. The status hold circuit drives an output element in response to the ON pulse outputted from the ON pulse generation circuit and holds driving status of the output element until a first OFF pulse is outputted from the first OFF pulse generation circuit. The second OFF pulse generation circuit generates a second OFF pulse in response to a protect operation signal and supplies this pulse to the status hold circuit, thereby to stop driving of the output element.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.

Abstract: An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a scaled load compensating circuit (12) comprising a plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) to SCF(n−1)). The compensating switches (SCT,SCF) are of type similar to the current steering switches (ST1 and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit D1 by the sum of the parasitic load capacitance of the current steering switches (ST1 or SF1) and the corresponding parasitic switching load capacitance of the corresponding compensating switch (SCTi or SCF1) is substantially similar for each driver circuit D1. Additionally, by virtue of the fact that the switching load capacitance, and in turn the switching loads presented to the driver circuits (D1) are similar, the driver circuits (D1) are therefore also similar to each other.

Abstract: An object of the present invention is to simply and rapidly adjust a delay time of a delayed clock signal in accordance with a change in frequency of an input clock signal. The present invention comprises: a pulse generating circuit for generating a pulse signal PULSE with a trailing edge of an input clock signal as a reference; an inverter chain consisting of a plurality of inverters; a pair of inverter chains for sequentially delaying output signals from the pulse generating circuit; a plurality of NOR gates for adjusting a delay time of each inverter in the inverter chain; and a plurality of NAND gates for similarly adjusting a delay time of each inverter in the inverter chain. Since the delay time of the delayed clock signal in a next cycle is set based on the pulse signal generated based on a trailing edge of the input clock signal, even if a cycle of the input clock signal varies, the delay time of the delayed clock signal can be rapidly changed in accordance with this variation.

Abstract: The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.

Abstract: This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Abstract: A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica.

Abstract: By utilizing a plurality of charge storing elements, a delay circuit may be reduced in size and cost. A delayed output signal is produced a predetermined time period after detection of an input signal by selectively charging and discharging each of a plurality of charge storage units either concurrently or successively and by detecting the charge level of each respective charge storage element. When the charge level of the respective charge storing elements indicates that a predetermined period of time has transpired since detection of the input signal, a delayed output signal is generated. This operation is performed in one embodiment by simultaneously charging two capacitors, comparing the voltage level of one capacitor with a reference potential, and inverting an output signal when the level reaches the predetermined reference potential. The second capacitor is used to tie the output to this level while the first capacitor discharges.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.