Abstract: A testing apparatus and method for detecting faults in encoders are disclosed. The testing apparatus includes a signal conditioning circuit board that receives an encoder signal and a central processing unit in communication with the circuit board and configured to: check for faulty amplitude, check for signal symmetry, check for signal offset, and/or check for signal transmission rate. The testing apparatus includes a real-time controller for real-time signal processing and fault detection.

Abstract: An adaptive identification system, for identifying a propagation system characteristic by an adaptive filter, includes a signal generator that generates an identification input signal including a frequency component of an integer multiple of a fundamental frequency and having a periodicity satisfying a PE condition, a setting unit that sets moving average time to a fundamental period of the identification input signal, and an adaptive algorithm execution unit that uses a moving average value and a diagonal matrix to update a coefficient of the adaptive filter, the moving average value being obtained by calculating a moving average of a cross-correlation vector of a vector of the identification input signal and an observation signal with the moving average time, and the diagonal matrix being obtained by diagonalizing a matrix obtained by calculating a moving average of an autocorrelation matrix of the vector of the identification input signal with the moving average time.

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.

Abstract: A failure state is correctly determined in a semiconductor device which operates in synchronization with a periodic signal. A first periodic signal generation unit generates a first periodic signal. A second periodic signal generation unit generates a second periodic signal from the first periodic signal. A third periodic signal generation unit generates a third periodic signal from the first periodic signal. A determination unit determines whether or not a frequency ratio between a pair of periodic signals in a group is substantially constant for each of a group of the first and second periodic signals, a group of the second and third periodic signals, and a group of the first and third periodic signals. In a case where the ratio is not substantially constant in two groups, a failure part specification unit specifies the periodic signal generation unit corresponding to the periodic signal commonly included in the two groups of the first, second, and third periodic signal generation units as a failure part.

Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

Abstract: The coding efficiency of an audio codec using a controllable—switchable or even adjustable—harmonic filter tool is improved by performing the harmonicity-dependent controlling of this tool using a temporal structure measure in addition to a measure of harmonicity in order to control the harmonic filter tool. In particular, the temporal structure of the audio signal is evaluated in a manner which depends on the pitch. This enables to achieve a situation-adapted control of the harmonic filter tool so that in situations where a control made solely based on the measure of harmonicity would decide against or reduce the usage of this tool, although using the harmonic filter tool would, in that situation, increase the coding efficiency, the harmonic filter tool is applied, while in other situations where the harmonic filter tool may be inefficient or even destructive, the control reduces the appliance of the harmonic filter tool appropriately.

Abstract: Disclosed is a method and a drive circuit. The method includes measuring a frequency of an input signal received by a drive circuit and driving a transistor device by the drive circuit based on the input signal such that a switching speed of the transistor is dependent on the measured frequency. The drive circuit is configured to receive an input signal, to measure a frequency of the input signal, and to drive a transistor device based on the input signal such that a switching speed of the transistor is dependent on the measured frequency.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.

Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

Abstract: An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal.

Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

Abstract: An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.

Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.

Abstract: A controller includes a difference detector that detects a difference between a switching timing of a first channel of a switching power supply including a plurality of channels, and a switching timing of a second channel of the switching power supply, the plurality of channels being coupled in common to an input power supply and performing switching operations in response to clock signals, and a timing adjuster that, based on a detection result of the difference detector, increases a difference between a timing of a clock signal supplied to the first channel and a timing of a clock signal supplied to the second channel when the difference between the switching timing of the first channel and the switching timing of the second channel is smaller than a first value.

Abstract: A multiphase mixer using a rotary traveling wave oscillator is disclosed. In addition to the oscillator, the mixer includes first and second mixer circuits. The rotary traveling wave oscillator generates a first set of N/2 phase and a second set of N/2 phases, where each phase has a frequency that is a factor of N/2 less than the incoming radio frequency signal. The first set of phases are sine signals and the second set of phases are cosine signals. The first mixer circuit generates a first down-converted signal from the first set of phases and the incoming rf signal. The second mixer circuit generates a second down-converted signal from the second set of phases and the rf signal.

Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.

Abstract: In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section.

Abstract: In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal.

Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

Abstract: In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section.

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract: A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to receive a second clock signal, synchronous with the first clock signal, at a third frequency and an output intended to deliver a third clock signal at a frequency alternately equal to the first value or the third value.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A frequency monitoring system comprises a plurality of circuit cards. Each circuit card, such as a primary multiplexer card and a backup or redundant multiplexer card, has an oscillator that provides a reference clock signal. On each circuit card, a respective frequency compare element is configured to receive a clock signal to be measured and to provide a frequency error signal indicating a frequency error of the clock signal relative to an average frequency of a plurality of reference clock signals. Accordingly, the frequency measurements for the circuit cards are based on the same reference frequency (e.g., the average frequency of the reference clock signals from the oscillators).

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock.

Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.

Abstract: A device for detecting and counting coughing events is provided. In one embodiment a sensor for sensing and transducing low frequency and high frequency mechanical vibrations, sends signals to a coincidence detector that determines if high and low signals coincide. In another embodiment, ultrasonic energy is introduced to the trachea and if Doppler shift in frequency is detected, association is made to a coughing event. In another embodiment a change in the impedance of the neck is considered associated with coughing event if correlated over time with a specific mechanical frequency sensed.

Abstract: A voltage detection device and a semiconductor device including the same are provided. The voltage detection device includes: a first clock generator which generates a first clock signal having a period that changes according to an external voltage; a second clock generator which generates a second clock signal having a predetermined period corresponding to a reference voltage; and a detector which detects a change of the external voltage by comparing the first clock signal with the second clock signal.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: A controller includes a difference detector that detects a difference between a switching timing of a first channel of a switching power supply including a plurality of channels, and a switching timing of a second channel of the switching power supply, the plurality of channels being coupled in common to an input power supply and performing switching operations in response to clock signals, and a timing adjuster that, based on a detection result of the difference detector, increases a difference between a timing of a clock signal supplied to the first channel and a timing of a clock signal supplied to the second channel when the difference between the switching timing of the first channel and the switching timing of the second channel is smaller than a first value.

Abstract: A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system.

Abstract: A control indication assembly. A first control mounted on a surface of a computer is coupled to a first sensor, to a first sensing circuit to send an electrical signal to the first control when a user-touch occurs to the first sensor, and to a first indicator to indicate an occurrence of said user-touch. A second control mounted on a surface of a display which is coupled to the computer is coupled to a second sensor, to a second sensing circuit to send an electrical signal to said second control when said user-touch occurs to the display, and to a second indicator to indicate an occurrence of the user-touch. The first and second control are configured such that the first and second indicator are synchronized to exhibit identical behaviors when the user-touch occurs to either the first control or the second control.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: Systems, algorithms, circuits, and methods for pattern detection of signature events in signal dynamics defined by instantaneous states of applied square-wave signals. Selected patterns may be recognized individually or in equivalence classes, and detection may be implemented via state or transition analysis. Varieties of conditions may be detected in parallel, including phase, ambiguity states, and frequency comparison. One embodiment realizes a real-time frequency comparator for asynchronous square-wave signals. Realizations detect various classes of symmetry conditions unique to enveloping events occurring for these classes of square-wave signal pairs. This approach provides feedback-free implementations operating over an extremely wide frequency range and does not require signals of quadrature form. A typical logic circuit implementation involves two to four flip-flops, or two-stage two-bit shift registers, and modest combinational logic.

Abstract: An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.

Abstract: A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signal. The harmonic frequency detector includes a counter for generating a first divided clock signal by dividing the frequency of the output clock signal by a first divisor. Additionally, the harmonic frequency detector includes a counter for generating a second divided clock signal by dividing the frequency of the reference clock signal by a second divisor. The harmonic frequency detector also includes a frequency comparator for generating an output indicating whether the frequency of the output clock signal is a harmonic frequency of the frequency of the reference clock signal based on the first divided clock signal and the second divided clock signal.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.