Abstract: Current sharing among bidirectional double-base bipolar junction transistors. One example is a method comprising: conducting current through a first bidirectional double-base bipolar junction transistor (first B-TRAN); conducting current through a second B-TRAN the second B-TRAN coupled in parallel with the first B-TRAN; measuring a value indicative of conduction of the first B-TRAN, and measuring a value indicative of conduction of the second B-TRAN; and adjusting a current flow through the first B-TRAN, the adjusting responsive to the value indicative of conduction of the first B-TRAN being different than the value indicative of conduction of the second B-TRAN.

Abstract: A gate driver circuit includes at least one driver configured to generate a first gate control signal for a first power disconnect switch and a second gate control signal for a second power disconnect switch in parallel with the first power disconnect switch, and logic configured to implement a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load coupled to the first and the second power disconnect switches. The gate driver circuit logic may also be configured to implement a delayed turn off time such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load. Corresponding power conversion circuits, electronic systems, and methods of power disconnect switch control are also described.

Abstract: A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

Abstract: An electronic circuit arrangement for use in an explosive area may include an electrical signal line, which connects an electrical input connector to an electrical output connector, and an electrical earth line, which can be or is electrically connected to the electrical signal line by at least one electrical earthing line. An inductive component and a semiconductor switch may be arranged in the at least one earthing line. The semiconductor switch may be switched between a closed state, in which the signal line is electrically connected via the at least one earthing line to the earth line, and an open state, in which this electrical connection is interrupted.

Abstract: Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Abstract: A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

Abstract: A gate control circuit including: a gate input arranged to receive an input gate feed signal; a gate output arranged to be connected, during normal operation, to at least one switching module for controlling current through a main circuit, the gate output being connected to the gate input; a power supply; and a switch connected between the power supply and the gate output, the switch being arranged to close as a response to a failure. A corresponding power module and method are also presented.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol includes a switch unit, first and second electronic switches, and first and second switch chips. When the switch unit outputs a high level signal to the first electronic switch, the connector transmits data according to LPC protocol. When the switch unit outputs a low level signal to the first electronic switch, the connector transmits data according to JTAG protocol.

Abstract: A liquid crystal display device includes a back light assembly that emits light on a liquid crystal panel; and an inverter that controls brightness of the light emitted from the back light assembly according to a difference between video data of at least three frames that are sequentially inputted to the liquid crystal panel.

Abstract: To detect opening/closing of a neutral detection hydraulic switch by a detection apparatus and detect breakage of a wiring line connected between the detection apparatus and the switch. Since a second contact and an ECU are connected to each other by two wiring lines, even if one of the wiring lines is broken, opening/closing of the neutral detection hydraulic switch can be detected through the remaining one of the wiring lines. Since different voltages are applied to the wiring lines through resistance type voltage dividing circuits, the occurrence of the wire breakage can be detected making use of the fact that the voltage detected by the ECU upon opening of the neutral detection hydraulic switch when one of the wiring lines is broken is different from the voltage when none of the wiring lines is broken.

Abstract: The invention relates to a method for statically balancing the loading of power semiconductor switches (S1, S2, S3) in a parallel circuit (1). To achieve this in prior art, switching instants of individual switches (S1, S2, S3) are adapted in the case of GTOs and current amplitudes of individual switches are adapted in the case of IGBTs. According to the invention, a primary pattern (4) of frame-switching pulses is predetermined for a total current (i) through the parallel circuit (1) and a secondary pattern (51, 52, 53) comprising more or fewer pulses than the primary pattern (4) is generated for at least one switch (S1, S2, S3). In contrast in conventional methods, the asynchronicity of the pulses enables a rapid redistribution of the loading between the parallel switches (S1, S2, S3), thus reducing or obviating the need for inductive suppressor circuits for limiting the current.

Abstract: A switching circuit (20) comprising first and second switch terminals (2,3) and a switch (21). The switch (21) comprises a first bipolar transistor (22), having a collector connected to the first switch terminal (2) and an emitter connected to the second switch terminal (3), and a second bipolar transistor (23), having an emitter connected to the first switch terminal (2) and a collector connected to the second switch terminal (3). The switch (21) can be turned on by supply of a control current to the base of either the first or the second bipolar transistor.

Abstract: An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Abstract: A switch in bipolar technology, comprising: including a first main transistor of a first type connecting an input terminal, intended to be connected to a first terminal of application of a D.C. supply voltage, to an output terminal intended to be connected to a load to be supplied; a second bipolar transistor of the same type as the first one, connected between said the input terminal and an input of a current mirror circuit having a copying output connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface area greater than the second one; and a circuit for biasing the second transistor consisting in including the copying of the output voltage of the switch on the collector of this second transistor.

Abstract: The present invention relates to an integrated circuit bidirectional switch formed from bipolar transistor devices, in which the saturation voltage is sought to be reduced. More specifically, an integrated NPN bipolar transistor is formed with oxide insulation, and the normal direction of current flow is from the emitter to collector, and an integrated PNP bipolar transistor is formed with oxide insulation, and the normal direction of current flow is from the collector to emitter.

Abstract: In order to provide a highly accurate and reliable temperature sensing circuit and method, a resistor (10a) having a positive temperature coefficient is connected between the gate terminal (4) and the insulated gate electrode (8a) of the voltage drive type semiconductor device (1a), and the temperature is sensed based on a voltage representing a voltage drop across the resistor in a circuit portion between the gate terminal (4) and the other terminal (5).

Abstract: A first amplifier circuit having a high frequency characteristic and a second amplifier circuit having a low frequency characteristic have first and second input terminals, respectively. The first and second amplifier circuits have first and second feedback resistors for self-bias and first and second switching elements capable of interrupting outputs of the amplifier circuits, respectively. Between the first and second input terminals, a third switching element is connected. A device for controlling on and off of the switching elements is provided in order that according to a signal input to the first and second input terminals, the signal is transmitted to either the first amplifier circuit or the second amplifier circuit. As a result, irrespective of whether the front end has one output terminal or two output terminals, the input circuit can be connected to the PLL synthesizer IC as it is by connecting the output to the first input terminal or to the two input terminals.

Abstract: A complementary multiplexer with low disabled output capacitance and method in which a plurality of switched buffers are packaged together to avoid the capacitance of a plurality of switched buffers applied to the printed-circuit board transmission lines.

Abstract: An improved current mode driver circuit uses N-type transistors in current mirrors to achieve higher speed operation at lower cost. A pair of matched low frequency P-type transistors provide a small amount of current to each side of the differential amplifier which comprise of only N-type transistors in a current mirror connection to amplify the current supplied thereto.

Abstract: Converters having a 1st power converter (1) on the mains systems side and a 2nd power converter (9) on the load side may have valve arms with insulated gate bipolar transistors (IGBTs) (T1, T2; T1', T2'). In order to be able to switch high currents, as are required in traction applications, a plurality of IGBTs (T1, T2) and (T1', T2') are operated electrically in parallel with one another. In order to avoid destruction or explosion of a module having IGBTs (T1, T2; T1', T2') of this type in the event of a short circuit, a fuse (Si1, Si2; Si1', Si2') is connected in series with each IGBT (T1, T2; T1', T2') on the cathode side thereof, which fuse blows when a predeterminable limit current intensity is exceeded, and thereby interrupts the short-circuit current. The current then flows only via the parallel-connected IGBT.

Abstract: A multi-stage analog bi-directional selector which has a low input impedance and cost. The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel.

Abstract: A transmit-receive switch which can be integrated. The receive diplexer of the switch comprises a parallel resonant circuit which can be completed or connected into the switch via a heterobipolar transistor. The transmit diplexer includes a series resonant circuit or a parallel resonant circuit which is connected into the switch circuit via a further heterobipolar transistor. Each of the heterobipolar transistors is rendered conductive or non-conductive via the applied HF power. That is, a high HF power, as is present in the transmission case, causes the respective transistor to become conductive and via the respective resonant circuits, cause the receive diplexer to become high impedance and block any signal, and cause the transmit diplexer to become low impedance and pass the high HF power substantially undampened.

Abstract: A switching circuit for outputting input and output signals from a single terminal includes an I/O signal interface circuit for forming a current path in parallel with a switch when a voltage at both terminals of the switch changes from high state to low state and for opening the current path when receiving a delay signal. An I/O signal separator provides the delay signal of predetermined time width when forming the current path to the I/O signal interface circuit and for blocking the current path during the delay period. Repeated and consecutive striking of a singular switch is ignored since only the first strike is effective. In addition, a display connected to a previously pressed switch remains continuously lighted when an interval between two consecutive struck different switches is shorter than the delay period.

Abstract: A CCD gate driver circuit provides an output drive signal in response to an input clock signal. The output drive signal is symmetrical, uses a minimum amount of power at high frequencies, and compensates for cross-coupling between CCD gates. An input circuit receives the input clock signal and converts it to current pulses on the transitions of the input clock signal. The current pulses are applied to a common input of a pair of complementary input transistors to switch conduction of the transistors. The control inputs of the input transistors are coupled to a reference voltage level. The outputs of the input transistors are coupled to respective current mirrors. The outputs of the current mirrors are in turn coupled to respective inputs of a pair of complementary output transistors that have a common output. A pair of voltage rails that define the voltage swing of the output drive signal are coupled to the respective control inputs of the output transistors.

Abstract: A power integrated circuit is pin-compatible with a three-terminal power MOSFET and contains integrated circuits to turn off the device in the event of an overcurrent or an over-temperature condition. Control power voltage V.sub.cc is applied through a first MOSFET connected between the gate pin and the gate electrode of the power device. A second control MOSFET is connected across the power device gate and source electrodes. The first control MOSFET is turned off and the second control MOSFET is turned on in response to a fault condition. The turn off of the first MOSFET limits the current sinked by the gate pin. A novel boot strap circuit is disclosed which permits the use of all N channel MOSFETs with an N channel power device, and a novel trimmable temperature shutdown circuit is provided. An integrated bipolar transistor is also integrated into the chip to prevent conduction of the P well/N epi diode formed in the device substrate.

Abstract: A low noise charge-pump circuit with low power consumption and operating in a cyclic mode comprises two current sources connected in parallel, and a current mirror for transforming the current supplied by one of the current sources and coupling it to the output of the other current source. Each of the current sources essentially comprises a transistor controlled from the output (VB) of a reference voltage generator via a respective transistor switch. The reference voltage generator essentially comprises a third transistor similar to the two first-mentioned transistors and in series with a further current source supplying a current Io, and means for making the current through the third transistor equal to the current Io.

Abstract: A power transistor (11) having a control electrode (16), a first electrode (17), a second electrode (181), and a kelvin electrode (19) is provided. The power transistor (11) comprises a plurality of transistors (12-15) coupled in parallel. Each transistor having a control electrode, a first electrode, and a second electrode coupled respectively to the control electrode (16) , first electrode (17) , and second electrode (18) of the power transistor (11). A plurality of first resistors (26-29) reduce oscillation and ringing, each first resistor is coupled between the kelvin electrode (19) and a second electrode of a transistor of the plurality of transistors (12-15). A plurality of second resistors (21-24) also reduces oscillation and ringing, each second resistor is coupled between the control electrode (16) and a control electrode of a transistor of the plurality of transistors (12-15).