Abstract: A system comprises a vibration sensor for generating a vibration signal on a turbomachine, a signal conditioner for conditioning the vibration signal, and a test signal generator for calibrating the signal conditioner. The test signal generator calibrates the signal conditioner with a test signal having a base frequency and a modulation frequency. The signal conditioner introduces a phase error into the vibration signal, and the signal conditioner introduces a phase shift into the test signal. A processor compensates for the phase error in the vibration signal by correcting the vibration signal based on the phase shift in the test signal, where the processor determines the phase shift in the test signal based on harmonic analysis of the modulation frequency.

Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.

Abstract: A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

Abstract: An apparatus relating generally to an analog multiplexer is disclosed. In such an apparatus, the analog multiplexer has first select circuits and at least one second select circuit. The first select circuits have respective input nodes and output nodes. The output nodes are all coupled to one another to provide an output node of the analog multiplexer. The first select circuits are coupled to a first supply voltage of a first supply domain. The at least one second select circuit is coupled to a second supply voltage of a second supply domain different from the first supply domain. The at least one second select circuit has an input port and an output port. The output port is coupled to an input node of the input nodes.

Abstract: An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.

Abstract: An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current.

Abstract: Input stages for use in multiplexing, and methods for using the same, are provided herein. An input stage includes an input terminal and an output terminal. A voltage input signal is accepted at the input terminal of the input stage. When the input stage is selected, a substantially unmodified version of the voltage input signal is presented at the output terminal of the input stage, when the input stage is selected. When the input stage is deselected, a rejection voltage signal is produced, where the rejection voltage signal is of substantially equal magnitude and opposite polarity to the corresponding voltage input signal in order to reject the voltage input signal and thereby present a substantially constant voltage at the output terminal of the input stage regardless of variations in the voltage input signal.

Abstract: A switching circuit (20) comprising first and second switch terminals (2,3) and a switch (21). The switch (21) comprises a first bipolar transistor (22), having a collector connected to the first switch terminal (2) and an emitter connected to the second switch terminal (3), and a second bipolar transistor (23), having an emitter connected to the first switch terminal (2) and a collector connected to the second switch terminal (3). The switch (21) can be turned on by supply of a control current to the base of either the first or the second bipolar transistor.

Abstract: A circuit configuration for mixing a differential desired signal with a differential local oscillator signal includes two difference amplifiers which are controllable on the input side by the desired signal and cross-coupled on the output side. Currents flowing through the difference amplifiers are switched by the components of the local oscillator signal in alternation. The circuit makes a lower supply voltage possible, given the presence of only two transistor levels.

Abstract: A BJT operating as a mixer has its collector biased at the knee of the IC vs VCE characteristic. A local oscillator voltage is applied to the base and an RF signal voltage is applied to the collector through a singled-ended emitter follower. The nonlinear curvature at the knee produces a beat frequency current. The base of the emitter follower can be fed from a current mirror or through an ohmic resistor. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Alternatively, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain. Sometimes, it is more desirable to invert the collector and the emitter, or to connect a normal transistor and an inverted transistor in parallel to optimize conversion gain.

Abstract: A combined multiplexer and switched gain circuit (250) that selectively multiplexes differential analog signals from a primary channel (20) and a diversity channel (22) in a diversity receiver system (10) to a single output. The circuit (250) is based on a current mode logic design where a plurality of separate conduction paths (278-284) are provided between a voltage line (266) and a current source (268). An output line (264) of the circuit (250) is coupled to each conduction path (278-284) so that the differential analog signals from the primary channel (20) and the diversity channel (22) can be selectively outputted to the circuit (250). Each conduction path (278-284) includes a gain device, such as degenerative resistor, that provides signal gain or no signal gain for that conduction path (278-284). Control signals are selectively applied to switching devices (310-324) and each conduction path (278-284) so that the conduction path (278-284) can be independently selected to provide the multiplexing.

Abstract: A high speed phase detector utilizes an integrated XOR/SUMMER/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/SUMMER/MUX circuit combines the functionality of two parallel XOR devices in series with a summer/multiplexer in a manner that reduces the number of gate delays associated with the input signals. In a practical implementation, the XOR/SUMMER/MUX circuit includes XOR arrangements having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/SUMMER/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Abstract: A high speed phase detector utilizes an integrated XOR/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/MUX circuit combines the functionality of an XOR device in series with a multiplexer in a manner that increases the bandwidth of the function. In a practical implementation, the XOR/MUX circuit includes an XOR arrangement having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Abstract: A multiplexer is provided that is symmetric in that substantially the same delay is experienced from any input of the multiplexer to the multiplexer output. It is realized that in conventional serial transmission systems, standard Current Mode Logic (CML) multiplexers are used which are asymmetric and exhibit different delays between select and data inputs. Because of these delays, conventional transmission systems experience jitter at high frequencies. To extend the operable range of communication systems, a symmetric multiplexer may be used which has substantially the same delay from any input to the multiplexed output, thus reducing jitter. For example, the multiplexer may be part of a communication system having a serial data transmission circuit.

Abstract: High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Abstract: A pulsing circuit for producing an output signal having a high amplitude pulse and a low amplitude pulse may comprise a current source for providing a high current signal and a low current signal. A gate circuit connected to the current source includes a trigger signal input that is responsive to a first trigger signal and a second trigger signal. The first trigger signal causes the gate circuit to connect the high current signal to a pulse output terminal whereas the second trigger signal causes the gate circuit to connect the low current signal to the pulse output terminal.

Abstract: A circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.

Abstract: A complementary multiplexer with low disabled output capacitance and method in which a plurality of switched buffers are packaged together to avoid the capacitance of a plurality of switched buffers applied to the printed-circuit board transmission lines.

Abstract: A switch (380) couples one group of MR channels (340, 342, 344) while decoupling another group of MR channels (340, 342 and 344). Thus, the parasitic capacitance associated with the decoupled group of MR channels does not limit the frequency response of the preamplifier.

Abstract: A multi-stage analog bi-directional selector which has a low input impedance and cost. The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel.

Abstract: The collector of the first transistor having the base to which the first signal input is supplied, is connected to the collector of the second transistor having the base to which the second signal input is supplied. The diode-connected third transistor is connected between the emitter of the first transistor and the output node, and the diode-connected fourth transistor is connected between the emitter of the second transistor and the output node. The first current mirror circuit supplies the current flowing in the constant current source to the emitters of the first and third transistors when the fifth transistor is in the ON state. The second current mirror circuit supplies the current flowing in the constant current source to the emitters of the second and fourth transistors when the sixth transistor is in the ON state.

Abstract: A switching apparatus for switching between channels within a read/write pre-amplifier circuit in a multi-channel magnetic media storage system switches between the channels and couples an active magnetoresistive sensor to receive biasing current and to a pre-amplifier circuit. When a read operation is requested from a specific channel within the magnetic media storage system, a control signal line corresponding to an appropriate magnetoresistive sensor is activated. Each channel includes a first corresponding transistor which is enabled by an appropriate control signal line, allowing current to flow through the first transistor to enable a second corresponding transistor that is coupled to the magnetoresistive sensor. Once enabled the second transistor couples the magnetoresistive sensor to a pre-amplifier stage and to receive biasing current.

Abstract: A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together.

Abstract: A first amplifier channel between an input and output includes an input transistor emitter and a first output transistor emitter connected together to form a first emitter pair. A current source is connected to the emitter pair via a transistor which is controlled by a latch. Programming the latch permits the channel to be turned on or off. The emitter pair is connected to a positive voltage through a resistor and to ground through a diode to force it to a controlled off voltage, which prevents signals from passing when the channel is off. There is a output driver amplifier in a feedback circuit. An outdisable circuit controls the voltage and current of the output driver amplifier to place the output in a state in which it appears electrically as an open circuit when the channel is off. Multiple programmable amplifiers can be combined to make a multiplexer, a selectable gain circuit, or a selectable attenuation circuit, all with high band width and high signal integrity.

Abstract: A first amplifier channel between an input and output includes an input transistor emitter and a first output transistor emitter connected together to form a first emitter pair. A current source is connected to the emitter pair via a transistor which is controlled by a latch. Programming the latch permits the channel to be turned on or off. The emitter pair is connected to a positive voltage through a resistor and to ground through a diode to force it to a controlled off voltage, which prevents signals from passing when the channel is off. There is a output driver amplifier in a feedback circuit. An outdisable circuit controls the voltage and current of the output driver amplifier to place the output in a state in which it appears electrically as an open circuit when the channel is off. Multiple programmable amplifiers can be combined to make a multiplexer, a selectable gain circuit, or a selectable attenuation circuit, all with high band width and high signal integrity.

Abstract: Audio bus receiver includes a pair of bipolar transistors each having a base coupled via a respective resistor to a respective bus receiver input terminal, each having an emitter that is diode coupled to a respective current source and each having a collector coupled via a respective load resistor to a source of reference potential. The emitters are coupled together via a gain control resistor and the collectors are coupled to an output terminal via a differential amplifier. Advantageously, the receiver avoids loading the bus under power-down conditions without requiring the use of stand-by power supplies. Additionally, high common mode rejection is achieved without need for precision matching of components and only a single supply voltage is required for operation.

Abstract: An analog circuit for multiplying a first input signal with a second input signal. The inventive analog circuit is capable of linear operation with a low voltage power source. A first pair of transistors is coupled as a first differential pair, and a second pair of transistors is coupled as a second differential pair. The first differential pair is coupled to the second differential pair in a manner that is similar to the corrections made between a first and second differential pair of a conventional Gilbert mixer. However, the emitter degeneration resistors of the present invention are not coupled to the collectors of a third differential pair, as is the case in conventional Gilbert mixers. Rather, the degeneration resistors of the present invention are coupled directly to the negative power supply terminal.

Abstract: The positive input terminal (1), the negative input terminal (2) and the differential amplifier (10) are connected to the voltage converting circuit (9a). The differential amplifier (10) is composed of the operational amplifier (6) and the resistors (5a, 5b, 5c and 5d). The voltage converting circuit (9a) includes NPN transistors (91, 92 and 93). The base of the transistor (91) is connected to the positive input terminal (1) and the base of the transistor (92) is connected to the reference potential input end (3) to which the reference potential (V.sub.x) is applied, respectively. The collectors of the transistors (91 and 92) are connected to the potential point (81) in common and the emitters are connected to the other end of the resistor (5a). The base of the transistor (93) is connected to the negative input terminal (2), the collector is connected to the potential point (81) and the emitter is connected to the other end of the resistor (5c).

Abstract: A signal switching circuit is provided to output signal switching between a first and a second input signal. The circuit includes a first analog switch transistor, a first switch transistor, a second analog switch transistor, a second switch transistor and a third switch transistor. The interference between the first input signal and the second input signal is reduced to a possible minimum through the invention.

Abstract: A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof.

Abstract: A switchable constant gain summer circuit (10) has been provided. The summer circuit selectively amplifies a plurality of input signals while maintaining a constant dc current flowing through a load which maintains a constant gain for the summer circuit. The summer circuit includes a plurality of amplifier circuits (12, 16) being respectively responsive to a plurality of input signals wherein each one of amplifier circuits has a control input and common first and second outputs for respectively providing first and second output signals. A plurality of control means (14, 18) responsive to a plurality of control signals is included for alternately providing first and second voltages to each one of the control inputs of the amplifier circuits. A load circuit (20) is coupled to the common first and second outputs of the amplifier circuits wherein a DC bias through the load circuit is substantially constant.

Abstract: A multiplexer configuration includes at least one first and one second group of transistors each including one first, one second and at least one third transistor. Current sources are connected to a first supply potential terminal and emitters of the transistors of each respective one of the groups are connected to one another and to a respective one of the current sources. A first resistor has one terminal connected to a second supply potential terminal and has another terminal and collectors of the first transistors of each respective one of the groups are connected to one another and to the other terminal of the first resistor. An output terminal is connected to the other terminal of the first resistor. Bases of the second transistors of each respective one of the groups are input terminals for a respective data signal. Bases of the third transistors of each respective one of the groups are terminals for a respective selection signal. The selection signals are mutually complementary.

Abstract: An integrated circuit in which closer matching or tracking of critical components, both active and passive, is achieved by time domain multiplexing of these critical components. Time domain multiplexing means that each of the components to be matched is alternately and sequentially, electronically switched between selected positions in the circuit. This is accomplished by continuous electronic movement or rotation of the critical components into or out of selected circuit positions to average in the circuit output any inherent errors due to variations resulting from electrical and physical characteristics appearing in the components. This arrangement is particularly useful in compensating for variations induced by the process used to create the components. This time domain multiplexing is especially useful in analog circuits employing complementary metal on silicon (CMOS) transistors, both field effect and bipolar in which component tracking is required for quality operation.