Abstract: A method for high speed switching comprises receiving voltage inputs at a bridge rectifier, receiving a logic input signal at an optical isolator and generating an output signal from the optical isolator based on the logic input signal, and driving a gate of a field effect transistor (FET) via the output signal of the optical isolator, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The method further includes limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

Abstract: A switching circuit includes a bridge rectifier to receive voltage inputs and an optical isolator to receive a logic input signal and generate an output signal based on the logic input signal. The high speed switching circuit also includes a field effect transistor (FET) with a source connected to a negative output of the bridge rectifier, a drain connected to a positive output of the bridge rectifier through a load, and a gate driven by the output signal of the optical isolator. First and second resistors connect the voltage inputs to the gate of the FET through first and second diodes. The first and second resistors and the first and second diodes limit current flowing to the gate of the FET. A Zener diode connected to the gate of the FET limits voltage to the gate of the FET below a maximum voltage rating of the FET.

Abstract: A switching circuit includes a bridge rectifier to receive voltage inputs across a load and an optical isolator to receive a logic input signal and generate an output signal based on the logic input signal. The high speed switching circuit also includes a field effect transistor (FET) with a source connected to a negative output of the bridge rectifier, a drain connected to a positive output of the bridge rectifier through a second load, and a gate driven by the output signal of the optical isolator. First and second resistors connect the voltage inputs to the gate of the FET through first and second diodes. The first and second resistors and the first and second diodes limit current flowing to the gate of the FET. A Zener diode connected to the gate of the FET limits voltage to the gate of the FET below a maximum voltage rating of the FET.

Abstract: The invention discloses a high speed switching solid state relay circuit with a switching section, a current limiting section and a voltage limiting section. The switching section comprises a bridge rectifier receiving the load voltage inputs, a MOSFET with a source connected to the negative voltage of the load through the bridge rectifier, a drain connected to the load voltage output, and a gate. The switching section further includes an isolator circuit comprising an optically-coupled LED. The isolator circuit is configured to receive a logic input signal and generate an isolated output signal based on the logic input signal, and the gate of the MOSFET is driven by the isolated output signal. The current limiting section includes a first set of resistors connecting the voltage drop across the load to the gate of the MOSFET through diodes. The voltage limiting section comprises a Zener diode connected to the gate of the MOSFET.

Abstract: An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.

Abstract: A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: An integrated circuit including a vertical power component having a terminal formed by a chip substrate of a first conductivity type, a control circuit thereof, the control circuit isolated from the substrate by an isolation region of a second conductivity type, and a protection structure against polarity inversion of a substrate potential. The protection structure includes a first bipolar transistor with an emitter connected to said isolation region and a collector connected to a reference potential input of the integrated circuit, a bias circuit for biasing the first bipolar transistor in a reverse saturated mode when the substrate potential is higher than the reference potential, and a second bipolar transistor with an emitter connected to the substrate and a base coupled to the isolation region for coupling the isolation region to the substrate through a high-impedance when the substrate potential is lower than the reference potential.

Abstract: A switch circuit includes an input terminal which receives an input signal and an internal circuit which executes a predetermined function. The switch circuit also includes a first switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving a control signal, a first electrode coupled to the input terminal, and a second electrode. The switch circuit also includes a second switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving the control signal, a first electrode coupled to the second electrode of the first switch element, and a second electrode coupled to the internal circuit.

Abstract: A communication interface circuit transfers signals between a TTL microcontroller and a RS232 device while avoiding level translation. The interface circuit includes two switch elements. A first switch element is connected between the TTL receive terminal and the ground supply. The second switch element includes a first node that is an electrical communication with the TTL transmit data terminal, the RS232 transmit data terminal and the RS232 receive data terminal, a second node in electrical communication with the first TTL power supply and a control node in electrical communication with the TTL receive data terminal. The interface circuit is configurable to a first switching state in which electrically connects the first TTL power supply terminal to the RS 232 receive data terminal.

Abstract: Minimal headroom, minimal area, multi-terminal current steering circuits for steering a current from a current source to any one of a plurality of outputs. The steering circuit provides controls to individual steering transistors so as to turn on the selected one of the plurality of steering transistors responsive to steering control signals. Minimal headroom is required, and beta dependent errors in the current output are minimized, by steering the current source through only a single transistor to the selected output. This also minimizes chip area. Alternate embodiments are disclosed and described.

Abstract: A high swing interface output stage integrated circuit for interfacing a data communications device with a data bus which may operate at voltage ranges outside the supply voltage of the interface circuit. An output terminal of the integrated circuit is coupled to a positive supply rail of the circuit through a substrate NPN transistor, and to a ground rail through first and second NMOS FETS. A third MOS FET also formed is coupled between the common connection of the first and second NMOS FETS and the gate of the second NMOS FET for holding the second NMOS FET off in the event of the voltage on the output terminal being driven below the ground voltage of the circuit. Other NMOS and PMOS FETS in the circuit control the operation of the circuit for determining the high and low states of the voltage on the output terminal.

Abstract: A multi-stage analog bi-directional selector which has a low input impedance and cost. The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel.

Abstract: A circuit for connecting a first circuit node to either a second or a third circuit node relative to the voltage potential on the third circuit node includes two bipolar transistors connected in series. The collectors of both transistors are connected to the first circuit node. The emitter of the first transistor is connected to the second circuit node and the emitter of the second transistor is connected to the third circuit node. Means are provided for maintaining the base of the second transistor at a constant, preset bias voltage.