Abstract: A drive circuit driving a first switching element, including: a first diode with a cathode terminal connected to a first switching element gate terminal; a second switching element with a first terminal connected to a first diode anode terminal, a second terminal connected to a first switching element gate terminal, a third terminal connected to a first switching element source terminal; a third switching element with a drain terminal connected to the first diode anode terminal, and a source terminal connected to the first switching element source terminal; a parallel circuit; and a drive transformer having a coil, one end connected to the drain terminal, the other end connected to the third switching element gate terminal, and connected to the third switching element source terminal, one end of the parallel circuit connected to one coil end, the second diode cathode terminal connected to the other end of the coil.

Abstract: A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.

Abstract: A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InxGa1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.

Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Abstract: Magnetic tunnel junction transistor devices and methods for operating and foaming magnetic tunnel junction transistor devices. In one aspect, a magnetic tunnel junction transistor device includes a first source/drain electrode, a second source/drain electrode, a gate electrode, and a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode. The magnetic tunnel junction includes a magnetic free layer that longitudinally extends between, and is overlapped by, the first and second source/drain electrodes. The gate electrode completely overlaps the magnetic free layer between the first and second source/drain electrodes. The magnetic tunnel junction transistor device switches a magnetization orientation of the magnetic free layer by application of a gate voltage to the gate electrode, thereby changing a resistance between the first and second source/drain electrodes through the magnetic free layer.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.

Abstract: A method for driving a field-effect transistor having a source section, a drain section and a gate section, includes applying a gate voltage to the gate section and causing the formation and/or maintenance of an electrically conductive channel between the source section and the drain section. After the channel has been formed, the gate section is disconnected from a gate voltage supply source which applies the gate voltage to the gate section.

Abstract: An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.