Abstract: Devices and methods of a field effect transistor device that include a source, a gate and a drain. The transistor includes a semiconductor region position is under the source, the gate and the drain. Such that the semiconductor region can include a gallium nitride (GaN) layer and an III Nitride (III-N) layer. Wherein the GaN layer includes a band gap, and the III-N layer includes a band gap. Such that the III-N layer band gap is higher than the GaN layer band gap. A sub-region of the semiconductor region is located underneath the gate and is doped with Mg ions at selective locations in the sub-region.

Abstract: A display device comprising: a plurality of pixels, each pixel including at least one sub-pixel; each sub-pixel comprising: a drivable visual segment, being operative to exhibit at least a first visible state and a second visible state; a first electrical potential setting section coupled with the drivable visual segment and with a first select terminal and a first data terminal, the first electrical potential setting section being operative to drive the drivable visual segment, at least from the first visible state to the second visible state; a second electrical potential setting section coupled with the drivable visual segment and with a second select terminal and a second data terminal, the second electrical potential setting section being operative to drive the drivable visual segment, independently from the first electrical potential setting section, at least from the first visible state to said second visible state.

Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.

Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its bulk.

Abstract: According to one embodiment, a gate control circuit includes a controller, a delay circuit, a power circuit, a boosting circuit, a first transistor, and a control circuit. The controller outputs first and second control signals based on a control signal from outside. The delay circuit delays the first control signal. The power circuit is capable of controlling a power supply voltage to be output based on the delayed first control signal. The boosting circuit is capable of boosting and outputting an input voltage. The first transistor has one end connected to an output node of the boosting circuit, and the other end grounded. The control circuit is capable of controlling a gate voltage of the first transistor based on the second control signal.

Abstract: A dimmer circuit for detecting a connected load type comprising a controller, a plurality of dimming transistors adapted to provide a dimmed hot output signal to a load, and a current sensor adapted to sense current levels of the dimmed hot output signal. The controller is adapted to store at least one load type current parameter associated with a dimming mode. The controller is further adapted to generate an asymmetric forward phase transistor drive signal with half cycles of one polarity having incrementally increasing dimming levels to drive the plurality of dimming transistors. The controller receives current levels from the current sensor and determines whether at least one of the received current levels satisfies at least one stored current parameter. When at least one current level satisfies at least one current parameter, the controller sets the dimmer to operate in a dimming mode associated with the satisfied current parameter.

Abstract: A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor.

Abstract: A Complementary Metal-Oxide-Semiconductor (CMOS) analog switch has a circuit structure such that when a supply voltage is applied, the CMOS analog switch biases voltages at both ends of a Metal-Oxide-Semiconductor Field Effect Transistor (MOS) device, which switches on upon application of supply voltage, to a substrate node of MOS, or biases the substrate voltage of MOS device to a ground voltage state during a switching-off operation. The substrate voltage of MOS device in floating state is still biased to the ground voltage state even when abnormal, high voltages are applied to both ends of the MOS device. As a result, threshold voltage and conduction resistance decrease compared to related analog switches, and frequency bandwidth increases.

Abstract: A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

Abstract: Techniques for improving the linearity of radio-frequency (RF) front-end switches. In an aspect, open-loop techniques are disclosed for superimposing the output voltage of one or more negative rectifiers on a negative substrate bias voltage to reduce the non-linearities associated with voltage-dependent substrate leakage current. In another aspect, closed-loop techniques are further disclosed for maintaining the substrate bias voltage close to a reference voltage. Exemplary embodiments of the circuit blocks are further described.

Abstract: A control circuitry (134) and a method for controlling a bi-directional switch (132) is provided. The bi-directional switch (132) having a control terminal (130) for receiving a control voltage (124) to control an on state and an off state of the bi-directional switch (132) and at least one semiconductor switch in a bi-directional main current path. The control circuitry (134) comprises an energy storage element (102), a coupling means (101) to couple the energy storage element (102) to a supply voltage to charge the energy storage element (102), and a control circuit (108) configured to receive power from the energy storage element (102) and configured to supply the control voltage having a voltage level being independent of the supply voltage when the energy storage element (102) is not coupled to the supply voltage. The coupling means (101) is configured for only coupling the 132 energy storage element (102) to the supply voltage when the bi-directional switch (132) is in the off state.

Abstract: A polycrystalline diamond abrasive element, particularly a cutting element, comprises a table of polycrystalline diamond bonded to a substrate, particularly a cemented carbide substrate, along a non-planar interface. The polycrystalline diamond abrasive element is characterized by the nonplanar interface having a cruciform configuration, the polycrystalline diamond having a high wear-resistance, and the polycrystalline diamond having a region adjacent the working surface lean in catalysing material and a region rich in catalysing material. The polycrystalline diamond cutters have improved wear resistance, impact strength and cutter life than prior art cutters.

Abstract: A load control device comprises a bidirectional semiconductor switch for controlling the amount of power delivered to an electrical load, and the bidirectional semiconductor switch further comprises two field effect transistors (FETs) in anti-series electrical connection. In the event that one of the FETs fails in a shorted state, and if the load control device is using a phase control dimming technique to control the load, the load control device may provide an asymmetric waveform to the electrical load. In order to determine whether this asymmetric waveform is present, a microprocessor of the load control device use voltage thresholds and/or offsets to monitor the voltage across the FETs. Thus, the microprocessor is operable to detect a fault condition of the load control device wherein the fault condition may comprise an asymmetry condition, or more particularly, a failure condition of one of the FETs.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: A polycrystalline diamond abrasive element, particularly a cutting element, comprises a table of polycrystalline diamond bonded to a substrate, particularly a cemented carbide substrate, along a non-planar interface. The polycrystalline diamond abrasive element is characterised by the nonplanar interface having a cruciform configuration, the polycrystalline diamond having a high wear-resistance, and the polycrystalline diamond having a region adjacent the working surface lean in catalysing material and a region rich in catalysing material. The polycrystalline diamond cutters have improved wear resistance, impact strength and cutter life than prior art cutters.

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract: A bidirectional switch includes a field-effect transistor having a first ohmic electrode, a second ohmic electrode and a gate electrode, and a control circuit for controlling between a conduction state and a cut-off state by applying a bias voltage to the gate electrode. The control circuit applies the bias voltage from the first ohmic electrode as a reference when a potential of the second ohmic electrode is higher than the potential of the first ohmic electrode, and applies the bias voltage from the second ohmic electrode as a reference when the potential of the second electrode is lower than the potential of the first ohmic electrode.

Abstract: In a duty ratio detecting apparatus, a duty ratio detecting circuit is constructed by first and second nodes, a load current supplying circuit for supplying first and second load currents to the first and second nodes, respectively, and a current switch connected to the first and second nodes. The current switch is operated in response to first and second complementary duty ratio signals. A duty ratio maintaining circuit is constructed by third and fourth nodes for receiving and maintaining voltages at the first and second nodes, respectively. A first switch is connected between the first and third nodes, and a second switch is connected between the second and fourth nodes. The load current supplying circuit is controlled by voltages at the third and fourth nodes.

Abstract: A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

Abstract: A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.

Abstract: The switch of this invention has two conduction terminals and basically consists of the parallel coupling, across the two conduction terminals, of a first N-channel MOS transistor and second P-channel MOS transistor. The first MOS transistor will be conducting when the signal applied to the conduction terminals has a first polarity, and the second MOS transistor will be conducting when the signal applied to the conduction terminals has a second polarity. Advantageously, if two unidirectional conduction circuit elements are respectively connected in series with the main conduction paths of the two MOS transistors, the drain/body junctions of the latter will never be conducting regardless of the way the switch is connected.

Abstract: A bidirectional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

Abstract: A bidirectional battery disconnect switch, i.e., a switch which is capable of blocking a voltage in either direction when open and conducting a current in either direction when closed, is disclosed. The switch includes a four-terminal MOSFET having no source/body short and circuitry for assuring that the body is shorted to whichever of the source/drain terminals of the MOSFET is biased at a lower voltage.

Abstract: A drive circuit for triggering a symmetrical bipolar transistor, the drive circuit having a balanced circuit connected to two operating electrodes of the symmetrical bipolar transistor. The balanced circuit includes two parts connected by their bases. Collectors of the two parts of the balanced circuit act on inverse balanced circuits which control a switching device which in turn controls the triggering of the symmetrical bipolar transistor.