Abstract: A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.

Abstract: A method for detecting a vehicle intrusion includes a first signal transmission process for alternately transmitting a first signal of a waveform through a first transmission module and a second transmission module at a predetermined period, a first intrusion determination process for analyzing a reflected wave received in response to the transmitted first signal to determine whether the intrusion occurred, a second signal transmission process for transmitting a second signal of a pulse waveform, upon detecting the intrusion as a result of the first intrusion determination process, a second intrusion determination process for analyzing a waveform of a reflected wave received in response to the transmitted second signal to determine whether the intrusion occurred, and transmitting a predetermined alarm message indicating that the intrusion occurred upon detecting the intrusion as a result of the second intrusion determination process.

Abstract: The inventive subject matter provides a circuit and a method for efficiently charging a battery. In one aspect of the invention, the circuit includes a constant current circuit configured to provide a direct current through the battery. The circuit also includes a pulsing current circuit that works with the constant current circuit and configured to simultaneously provide a series of pulsed current to the battery. In some embodiments, the series of current pulses includes constructive resonant ringing that is constructive with respect to the charging of the battery.

Abstract: Disclosed is an electronic timepiece including a rotary switch, a rotation detection unit which detects a rotation of the rotary switch every time the rotary switch rotates for a predetermined rotation angle, a determination unit which determines as a continuous detection when a number of times the rotation detection unit detects the rotation is a predetermined number of times or greater before a preset unit time have elapsed from a detection timing, the predetermined number of times being 2 or more and a control unit which executes a predetermined function when the determination unit determines as the continuous detection.

Abstract: Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator.

Abstract: A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration.

Abstract: A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs.

Abstract: A system for simulating biofidelic signals includes a transducer and a neural transmitter port. The transducer is affected by a parameter and provides an alternating electrical signal based on an effect of the parameter. The neural transmitter port receives a processed electrical signal and outputs the processed electrical to a neural transmitter. The system further includes an input portion, a band-pass filter, and an integrate-and-fire mechanism. The input portion outputs a first signal based on the alternating electrical signal. The band-pass filter outputs a first filtered signal based on the first signal. The integrate-and-fire mechanism generates the processed electrical signal based on the first filtered signal.

Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.

Abstract: The frequency decision device determines frequency of the measured rectangular signal by simple and easy means. The frequency decision device inputs the measured rectangular signal that frequency (or period) changes dynamically. It generates a rectangular reference signal of predetermined on width ? synchronizing to the edge based on a positive going edge of this measured rectangle signal. And it watches the order of measured rectangle signal and falling edges of the rectangular reference signal. When this sequential order reversed, it detects that length of the ON time of ON time of the measured rectangle signal and the measured rectangular signal reversed.

Abstract: A device for detecting and counting coughing events is provided. In one embodiment a sensor for sensing and transducing low frequency and high frequency mechanical vibrations, sends signals to a coincidence detector that determines if high and low signals coincide. In another embodiment, ultrasonic energy is introduced to the trachea and if Doppler shift in frequency is detected, association is made to a coughing event. In another embodiment a change in the impedance of the neck is considered associated with coughing event if correlated over time with a specific mechanical frequency sensed.

Abstract: A signal preprocessing device is disclosed, which is integrated into a structure-borne sound sensor or into an acceleration sensor for sensing structure-borne sound, or which is connected at the input end to at least one sensor of this type and is connected at the output end to at least one signal channel that is connected to at least one central electronic control unit, and wherein the signal preprocessing device has at least one filter module having at least two bandpass filters. A method for preprocessing structure-borne sound sensor signals is also disclosed, in which a filtering operation is carried out in which at least two frequency bands, which are at least to a certain extent part of the structure-borne sound spectrum, are transmitted. Use of the above device in electronic motor vehicle security systems, in particular safety systems, in particular in vehicle occupant protection systems and/or passenger protection systems is also disclosed.

Abstract: Method for decoding a signal sent over a bandwidth-expanding communication system, where both channel estimation and signal detection are carried out on a set of samples generated by sampling the received signal at a sub-Nyquist rate, thus allowing for a significant reduction of the complexity of the sampling device of receivers using said method, as well as a significant reduction of their computational requirements.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed.

Abstract: A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to a node to be compensated; a first resistance coupled between an output of the amplifier and the replica circuit; a second resistance coupled between the output of the amplifier and the node to be compensated; and wherein the replica leakage current is subtracted from the node to be compensated.

Abstract: An object is to provide a resonator and a vibrator with a high Q value in which dissipation of vibration energy in vibration of the vibrator is small, and a thickness of a support part of the vibrator of a beam structure is made thicker than a thickness of the vibrator and the support part is formed in axisymmetry with respect to a length direction of a beam. By this configuration, brittleness of the support part is improved and loss of vibration energy from the support part is reduced and also loss of vibration energy resulting from surface roughness of a surface of the vibrator can be reduced, so that a resonator having a high Q value can be provided.

Abstract: A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.

Abstract: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

Abstract: A circuit drives an LED array and controls the brightness of the LED array by regulating the current flowing through the array. The LED array is driven by a pulse-shaped current of which the mean value is regulated with at least one or two of the following types of modulation: frequency modulation, pulse-width modulation, and amplitude modulation.

Abstract: A system and method for detecting islanding in a Distributed Generation utility grid is described. In some examples, the system, via an inverter, injects a frequency disturbance to a location of the utility grid associated with a DG generator, measures both the frequency error due to the disturbance and the frequency drift of the location of the utility grid, and determines islanding based on a maximum value of the frequencies. In some cases, the system is able to reduce or minimize the Non-Detection Zone of the inverter by detecting islanding without always relying on a detectable frequency error due to an injected waveform.

Abstract: To provide a broadband circuit from which a desired circuit characteristic is stably obtained over a wide frequency band with a small number of circuit devices and which can be easily designed. In the case of the broadband circuit to which a circuit device is connected through a transmission line including a signal transmission conductor, grounding conductor, and dielectric present between these conductors, an LILC 13 having a four-terminal line structure in which a pair of conductors are faced each other, having an impedance lower than that of a conductor connected to any terminal, and using a frequency band of an electromagnetic wave whose wavelength is shorter than a length approximately four times of the length of the circut device as an object frequency band is inserted into the transmission line and used as a low impedance device to the electromagnetic wave of the object frequency band.

Abstract: A digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived, for example, from a communications signal. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching frequencies. The converter includes at least one Soft-Start (SS)/Frequency-Select(FS) input, at least one oscillator enable input, and an oscillator having at least one control input. Soft-start programming is linked to the frequency selection of the converter. An external capacitor connected between the SS/FS input and ground is employed to program the soft-start time, and the switching frequency generated by the oscillator is selected via the state of the SS/FS input.

Abstract: An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal during a predetermined number of cycles of the external signal, or the number of cycles of the external signal during a predetermined number of cycles of the clock signal; (c) store a trim value in the integrated circuit, the trim value having been determined on the basis of the determined number of cycles; and (d) use the trim value to control the internal clock frequency.

Abstract: A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

Abstract: The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

Abstract: A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.

Abstract: A bi-directional semiconductor light source is formed that provides emission in response to either a positive or negative bias voltage. In a preferred embodiment with an asymmetric injector region in a cascade structure, the device will emit at a first wavelength (&lgr;−) under a negative bias and a second wavelength (&lgr;+) under a positive bias. In other embodiments, the utilization of an asymmetric injector region can be used to provide a light source with two different power levels, or operating voltages, as a function of the bias polarity.

Abstract: A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Abstract: A method and system for distinguishing valid DTMF signals from spurious DTMF noise includes detecting signals having a first signal component indicative of DTMF signals and having a second signal component having frequencies unrelated to DTMF frequencies. The second component is utilized in isolation from the DTMF frequencies of the first signal component. The analysis includes determining a signal level representative of the second signal component. If the signal level exceeds a predetermined threshold level, the first signal component is determined to be spurious noise. On the other hand, if the signal level is below the threshold level, the first signal component is passed to a DTMF-responsive system, such as a voicemail system or a voice response unit. Optionally, the operation includes requesting confirmation of the signal of interest, if the signal level of the second signal component falls within a range which includes the threshold level as its upper limit.

Abstract: Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: A first amplifier circuit having a high frequency characteristic and a second amplifier circuit having a low frequency characteristic have first and second input terminals, respectively. The first and second amplifier circuits have first and second feedback resistors for self-bias and first and second switching elements capable of interrupting outputs of the amplifier circuits, respectively. Between the first and second input terminals, a third switching element is connected. A device for controlling on and off of the switching elements is provided in order that according to a signal input to the first and second input terminals, the signal is transmitted to either the first amplifier circuit or the second amplifier circuit. As a result, irrespective of whether the front end has one output terminal or two output terminals, the input circuit can be connected to the PLL synthesizer IC as it is by connecting the output to the first input terminal or to the two input terminals.

Abstract: Disclosed is a high voltage generator circuit of the charge pump type. The rate of operation of this pump is set by a sequence of piloting signals produced out of a clock signal. This clock signal is itself produced by an oscillator. A frequency servo-link is set up between the clock signal produced by the oscillator and the running of the sequence in order to produce a clock signal with a frequency that is equal to the maximum permissible frequency for low supply voltages while at the same time limiting this frequency from a given supply voltage threshold onwards.

Abstract: A driver for a power transistor (a MOSFET or IGBT) uses a transformer to isolate the power supply from the control signal, but uses very low power components on the isolated side to allow use of a physically small transformer. The control signal is one of two frequencies, and the isolated side of the driver includes a circuit for detecting which of the two frequencies is present. One frequency is preferably twice as much as the other. The output of the frequency detection circuit switches between low and high states depending on the frequency present, and the output of this circuit is connected to the input of a transistor driver circuit which charges the gate of the power transistor.

Abstract: A method and an apparatus in testing whether the frequency of an incoming signal is higher or lower than a predetermined value. The method only demands a capacitor (C), a resistor (R), a field effect transistor (Q) and a constant current generator (I). Because the included capacitor only needs to have a small value, a circuit design according to the method is very suitable for integration, for example, in form of a monolithic integrated circuit for frequency control in connection to DC/DC converters.

Abstract: A frequency and phase comparator has a first flip-flop and a second flip-flop. Logical calculation between the outputs of these flip-flops is performed by an AND circuit, and the first and second flip-flops are reset by the output of the logical calculation. The first and second flip-flops receive periodic signals at their clock terminals. When the periods of the output pulses of the first and second flip-flops are short, a circuit driven by the pulses sometimes cannot operate correctly. To prevent this, a pulse generating circuit is provided which receives a first periodic signal and a second periodic signal to generate a pulse signal of a predetermined width, and the pulse signal is added to the outputs of the first and second flip-flops.

Abstract: A programmable frequency synthesizer includes a first memory (e.g., ROM) for storing a plurality of pre-programmed frequencies, a second memory (e.g., RAM) for storing at least one user input programmable frequency, and dual purpose frequency synthesizer inputs for providing command address information to select one of the pre-programmed frequencies from the first memory and for providing serial data representing a user input programmable frequency to be stored in the second memory. The frequency synthesizer further includes a control input and decoder for directing the address information and the user input programmable frequency data to the first or second memory, respectively.

Abstract: A frequency-controlled circuit for automatically detecting a center frequency of a received signal whose frequency is shifted includes a frequency control unit for receiving the input signal and changing the frequency of the received signal into another frequency, a demodulating unit for demodulating a signal outputted from the frequency control unit, an incoming detecting unit for detecting whether a demodulated signal outputted from the demodulating unit is proper or improper and a level detecting unit for dividing a frequency band of the signal, obtained in the frequency control unit by adding a receive frequency band of the received signal to the center frequency of the received signal or subtracting the center frequency thereof from the receive frequency band thereof, into a plurality of narrower frequency bands and detecting respective power values of the divided frequency bands.

Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance wit

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: A frequency discriminator which generates an output signal characteristically representative of a predetermined frequency spectrum of an input signal, but insensitive to variations in the amplitude and spectral width thereof is disclosed. The frequency discriminator is adaptable for use in a radar receiver clutter tracking loop to improve the filtering of clutter signals from the radar returns by maintaining a measured centroid frequency of the clutter signal spectrum substantially at a desired frequency with a loop response which is invariant to both amplitude and spectral width of the clutter signals. More specifically, the frequency discriminator when included in a clutter tracking loop of a radar receiver discriminates from the clutter spectrum a plurality of frequency signals in accordance with a preselected sequence and computes the amplitudes thereof to generate a corresponding sequence of amplitude signals.

Abstract: Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.

Abstract: The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer. A bus clock controlling apparatus according to the present invention includes power mode detecting means detecting a current power mode, the power mode indicative of which power source supplies the portable computer with electric energy; and clock adjusting means adjusting frequency of an applied clock from a clock generator based on the detected power mode by said power mode detecting means, and applying the frequency-adjusted clock to one or more controlling devices. Due to this invention, an electric energy stored in a battery equipped in a portable computer is saved, as a result, the battery life is extended.