Multiple Collector Transistor Patents (Class 327/481)
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Patent number: 6729318Abstract: An electronic component, such as an IGBT, that presents a control terminal for receiving a stepwise control signal and at least one other terminal adapted for reaching a given voltage level by effect of the application of the step signal, with the possibility of overshoot occurring; and a damping resistive element interposed between the control terminal and the at least one other terminal. The damping resistive element shows a current saturated behavior correlated to voltage increase applied at the terminals towards the given voltage level, thus eliminating the risk of occurrence of overshoot in the voltage of the IGBT collector, and preventing the undesired re-ignition of the IGBT when it is in a cut-off condition, by inducing an overvoltage on the collector terminal.Type: GrantFiled: November 21, 2001Date of Patent: May 4, 2004Assignee: STMicroelectronics S.r.l.Inventor: Antonino Torres
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Patent number: 6459321Abstract: Gate protection clamping circuits and techniques with controlled output discharge current are provided. Circuits and methods according to the invention are implemented to relatively rapidly disengage single or multiple loads from a power supply without creating thermal overload. This is accomplished by first rapidly shutting OFF the power device coupling the power source to the load, and then further discharging the output capacitance with a substantially smaller, preferably regulated, current. Additional external devices may be added if faster discharge of the output capacitance is desired.Type: GrantFiled: June 28, 2001Date of Patent: October 1, 2002Assignee: Linear Technology CorporationInventor: Mark A. Belch
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Publication number: 20020062825Abstract: An electronic component, such as an IGBT, that presents a control terminal for receiving a stepwise control signal and at least one other terminal adapted for reaching a given voltage level by effect of the application of the step signal, with the possibility of overshoot occurring; and a damping resistive element interposed between the control terminal and the at least one other terminal. The damping resistive element shows a current saturated behavior correlated to voltage increase applied at the terminals towards the given voltage level, thus eliminating the risk of occurrence of overshoot in the voltage of the IGBT collector, and preventing the undesired re-ignition of the IGBT when it is in a cut-off condition, by inducing an overvoltage on the collector terminal. FIG. 5 is the one selected.Type: ApplicationFiled: November 21, 2001Publication date: May 30, 2002Applicant: STMicroelectronics S.r.l.Inventor: Antonino Torres
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Patent number: 6081139Abstract: The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.Type: GrantFiled: September 25, 1997Date of Patent: June 27, 2000Assignee: Intel CorporationInventors: Carl F. Liepold, James T. Doyle
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Patent number: 5717348Abstract: A edge detector for the production of output signal in a manner dependent on positive and negative edges of a square wave signal comprises a differential amplifier with two base-coupled transistors (Q1, Q2). Each emitter of such transistors is connected via a constant current source (S1 and, respectively, S2) with a supply voltage line (10) and the emitter currents of the transistors are split up between two collectors, of which the first ones are connected with one another and, via a third constant current source (S3), with ground (12). Two output loops each comprise a series circuit composed of a resistor (R3, R4) and the collector-emitter path of an output transistor (Q3, Q4) between ground (12) and the supply voltage line (10). In the case of each of such output transistors (Q3, Q4) the base is connected in each case with a second collector of the base-coupled transistor (Q1, Q2) so that the switching state of the output transistors (Q1, Q2) is set by the voltage at each second collector.Type: GrantFiled: June 7, 1995Date of Patent: February 10, 1998Assignee: Texas Instruments Deutschland GmbHInventor: Helmut Kiml
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Patent number: 5703520Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.Type: GrantFiled: April 1, 1996Date of Patent: December 30, 1997Assignee: Delco Electronics CorporationInventors: John Mark Dikeman, Mark Wendell Gose
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Patent number: 5532627Abstract: A stackable voltage comparator circuit that may be used in an analog voltage address decoder circuit for performing voltage window comparisons. The voltage comparator circuit includes a plurality of voltage comparator circuit cells, each of which includes a differential input stage made up of a pair of transistors which receives a current source. A first comparator circuit cell includes a differential input pair of transistors with one of the transistors having a first collector and a second collector, with the second collector being coupled to an output line. The first comparator circuit cell compares an input window with a first threshold voltage and produces an output at the output line. A second comparator circuit cell compares the input voltage with a second threshold voltage and includes a second differential input pair of transistors.Type: GrantFiled: April 14, 1995Date of Patent: July 2, 1996Assignee: Delco Electronics CorporationInventors: Mark B. Kearney, Dennis M. Koglin
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Patent number: 5514949Abstract: A current mirror having at least one pnp-transistor and providing overvoltage protection has three collectors designed as partial collectors. Two of the partial collectors and the base are linked to a reference-current source and the other partial collector is linked to a terminal connection of the current source to be protected from overvoltage. In the event of an overvoltage across the terminal connection, an emitter is formed by the partial collector linked to this terminal connection which limits the received current in proportion, conditional upon the topology, with the mirror-reference current.Type: GrantFiled: January 21, 1994Date of Patent: May 7, 1996Assignee: Robert Bosch GmbHInventors: Guenter Bross, Gerard Byrne
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Patent number: 5453712Abstract: A subcircuit for discharging a capacitor at a preselected rate incorporates a first transistor and a second transistor connected with the emitter of the first transistor providing current to the collector of the second transistor. The base of the first transistor is connected to a capacitor to be discharged at a preselected rate. The base current of the first transistor discharges the capacitor as a function of the base current provided to the second transistor. In order to provide a current of very small magnitude to the base of the second transistor, a plurality of lateral PNP transistors are connected in a plural stage arrangement in order to take advantage of the current dividing characteristic of lateral PNP transistors. A collector of one lateral PNP transistor is connected to the emitter of another so that each stage of the subcircuit reduces the output current by a very precise ratio.Type: GrantFiled: January 25, 1995Date of Patent: September 26, 1995Assignee: Honeywell Inc.Inventor: Peter G. Hancock
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Patent number: 5424676Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.Type: GrantFiled: January 29, 1993Date of Patent: June 13, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventor: Henry Z. Liwinski