Abstract: It is an object of the present invention to provide a buffer circuit that reduces a reverse voltage applied to transistors being a complementary pair during turn-on and turn-off. A buffer circuit is a buffer circuit that turns on and turns off a switching element and includes a drive-side element that has an end connected to a base of a drive transistor and a sink-side element that has an end connected to a base of a sink transistor. The drive-side element and the sink-side element are respectively a drive-side diode and a sink-side diode, or a drive-side capacitor and a sink-side capacitor.

Abstract: A circuit for driving a capacitive load using a booster having a low power consumption, which amplifies spike-like signals at high speeds and produces a large voltage and a large current, and wherein two transistors 104 and 111 are connected in series across a first power source H1 and a second power source L1 having a potential lower than that of the first power source. An output terminal OUT is provided at a portion where the two transistors are connected together, and the first transistor 104 connected between the first power source and the output terminal has a complementary relationship to the second transistor 11 connected between the output terminal and the second power source.

Abstract: A totem pole driver circuit for driving N-channel Field Effect Transistors and Insulated Gate Bipolar Transistors, using a binary to decimal decoder/demultiplexer or a decoding analog multiplexer integrated circuit and signal transformers for switching the totem pole transistors, and employing a dead-time delay in the logic circuit to protect the transistors during switching.

Abstract: A totem pole driver with cross conductive protection and default low impedance state output employs a totem pole output formed by top and bottom output transistors. A first circuit path switches the bottom output transistor on or off in response to a switching signal. A second circuit path, slower than the first circuit path, switches the top output transistor on in response to the switching signal after the bottom output transistor is switched off. A third circuit path switches the top output transistor off in response to a sync signal known to lead the switching signal. An emergency voltage supply is made available to hold the bottom output transistor on and the top output transistor off if the regulated circuit voltage is lost.

Abstract: A cascode circuit includes a source-grounded input NMOS transistor having a gate connected to an input terminal and a drain connected through an output NMOS transistor to an output terminal. An amplification circuit is constructed by a gate-grounded third NMOS transistor having a source connected to the drain of the input transistor, a current mirror circuit consisting of PMOS transistors having an input current path connected to a drain of the third transistor, and a current source connected to an output current path of the constant mirror circuit as a load. An output from the amplification circuit is fed back to a gate of the second transistor. With this arrangement, the cascode circuit can maintain a high output impedance until a minimum output signal voltage reaches around 0.5 V, and can also have a minimum working supply voltage of about 2 V, and at the same time, a circuit construction suitable for IC in the CMOS process.

Abstract: A power switching circuit includes a power switching NPN transistor (1) having its collector electrode coupled to a reference potential terminal (17) and its emitter electrode coupled to an output terminal (7). A driver circuit (5) is provided having an input coupled to a supply terminal (6) and a driving current output coupled to the base electrode of the power transistor (1). A PNP transistor(4) has its emitter electrode coupled to the output terminal(7), its base electrode coupled to a reference voltage terminal (9) for receiving, in operation, a voltage which is positive relative to the reference potential and its collector electrode coupled to the base electrode of an NPN transistor (2). The NPN transistor (2) has its collector electrode coupled to the collector electrode of the power transistor (1) and its emitter electrode coupled to the base electrode of the power transistor (1).