Abstract: A switched capacitor is provided. The switched capacitor includes a pair of parallel component stacks. Each stack is connected to a common top node and a common bottom node. Each stack includes a BJT. Each stack further includes a first resistor in series with the BJT and having a first side connected to a collector of the BJT at an intermediate node in a same one of the stacks and a second side connected to the common top node. Each stack also includes a capacitor having a first side connected to the intermediate node and a second side for providing an impedance. Each stack additionally includes a second resistor having a first side connected to a base of the BJT to prevent base-current surge in the BJT and a second side connected to a switch base control signal that selectively turns the BJT on or off.

Abstract: A matrix converter includes a plurality of switching elements and is adapted to receive a multi-phase alternating current (AC) input signal having an input frequency and to generate a multi-phase AC output signal having an output frequency. The phases of the input signal are sorted as a function of their instantaneous voltage amplitude (60). A reference signal is generated from output reference voltages that correspond to each phase of the output signal (56). Duty cycles are calculated for each phase of the output signal based on the sorted input signal phases and the reference signal (62). Switching functions, which each control one of the switching elements, are then generated based on the duty cycles for each phase of the output signal (64, 66).

Abstract: A driver circuit is provided for enabling a transistor collector-emitter path to be used as a broadband periodic switch. The broadband driver circuit controls the magnitude of the transistor base-emitter current in order to enable a CLOSED switch state and to simultaneously control the magnitude of the transistor base-emitter reverse-bias voltage in order to enable the OPEN-switch state. The precise control of these parameters minimizes base-charge storage and prevents reverse-breakdown failure.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.

Abstract: A write driver for a two-terminal inductive load comprises an H-bridge switching circuit and a push-pull driver circuit. The H-bridge switching circuit responds to a first mode to conduct a current in a first direction through the inductive load and responds to a second mode to conduct the current in a second direction through the inductive load. The push-pull driver circuit responds to the first mode to push a charge current into a first control node of the H-bridge and responds to the second mode to pull a discharge current from the first control node. In one form, the write driver includes a second push-pull driver circuit responsive to the first mode to pull a discharge current from a second control node and to the second mode to push a charge current into the second control node.

Abstract: A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.