Abstract: A system including a burner configured to be coupled to a fuel line to deliver fuel to the burner and an igniter positioned adjacent to the burner and configured to ignite fuel emitted by the burner. The system further includes a valve configured to control a flow of fuel through the fuel line and a control module operably coupled to the igniter and to the valve. The control module is configured to send a signal to the igniter and to close the valve if a quality of a return electrical signal from the igniter is below a predetermined value.

Abstract: A wireless power receiving circuit includes a transistor based rectifier receiving an AC input voltage, and control logic receiving an overvoltage signal. The control logic generates control signals for controlling turn on of transistors within the transistor based rectifier based upon the overvoltage signal so as to cause the transistor based rectifier to produce a rectified output voltage from the AC input voltage. A comparator compares the rectified output voltage to a reference voltage and asserts the overvoltage signal if the rectified output voltage is greater than the reference voltage. In response to assertion of the overvoltage signal, the control logic asserts the control signals to simultaneously turn on all transistors of the transistor based rectifier.

Abstract: Methods and apparatuses for tuning source impedance for at least a portion of a receive path in a radio frequency front-end. An exemplary circuit generally includes a first tunable resonant circuit having an output coupled to an input of the at least the portion of the receive path and a second tunable resonant circuit having an input coupled to the output of the first tunable resonant circuit and to the input of the at least the portion of the receive path. The circuit also includes a first control input coupled to the first tunable resonant circuit and configured to adjust an impedance of the first tunable resonant circuit based on a frequency response of an output of the at least the portion of the receive path, and a second control input coupled to the second tunable resonant circuit and configured to adjust an admittance of the second tunable resonant circuit.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: Systems and methods related to single molecule switching devices are disclosed. One example method can include the step of applying a tunneling current across a tunneling junction. The tunneling junction can include an endohedral fullerene that includes a fullerene cage and a trapped cluster or a trapped atom. Such a method can also include exciting one or more internal motions of the trapped cluster or the trapped atom based at least in part on the tunneling current, and changing the conductance of the endohedral fullerene based at least in part on the one or more excited internal motions. One or more electronic processes can be controlled based at least in part on the changed conductance of the endohedral fullerene.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: A method and an arrangement are provided for balancing the switching transient behavior of parallel connected power semiconductor components. The method includes providing a switch signal to the parallel connected power semiconductor components for changing the state of the components, forming control signals for each of the parallel connected components from the switch signal, and determining, during the change of state of the power semiconductor component, the voltage induced to an inductance in the main current path of the component in each of the parallel connected components. The method also includes comparing each of the induced voltages with a predetermined threshold voltage, measuring time differences between the time instants at which the induced voltages crosses the threshold voltage, and modifying one or more of the control signals on the basis of the measured time differences in the respective following state change for balancing the switching transient behavior.

Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal.

Abstract: Method for operating a converter circuit with voltage boosting with N half-bridges, which in each case can be connected by their center connection to a phase of an N-phase generator and at an end side are connected in parallel with a series circuit formed by two capacitances, wherein each half-bridge contains a Top switch and a Bot switch, in which, in a PWM method with a fixed period duration at the beginning of the period duration, all the TOP switches are simultaneously switched on for the duration of a TOP switched-on interval. After half the period duration all the BOT switches are simultaneously switched on for the duration of a BOT switched-on interval wherein the TOP switched-on interval, and the BOT switched-on interval amount at most to half the duration of the period.

Abstract: It is possible to reliably prevent two switching elements comprising a half-bridge circuit from turning ON simultaneously even when two pulse signals allowing both the two switching elements to turn ON are input thereto. A first drive signal is allowed to be output from a first output terminal 4 to a P-type MOSFET 10 based on a first pulse signal and a second pulse signal, and a second drive signal is allowed to be output from a second output terminal 5 to an N-type MOSFET 11 that operates as a second switching element based on the first pulse signal and the second pulse signal, and a protecting circuit 20 is configured to allow at least one of the P-type MOSFET 10 and the N-type MOSFET 11 to turn OFF.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: It is presented a gate driver circuit for driving an electric switch, the switch being arranged to control a main current using a gate signal. The gate driver circuit comprises: a non-linear capacitor means having a lower capacitance when an applied voltage is under a threshold voltage and a higher capacitance when an applied voltage is over the threshold voltage, wherein the non-linear capacitor is arranged to be connected between a high voltage connection point of the switch and a connection point for the gate signal; a current change rate sensor, the current change rate sensor being configured to detect changes in a main current of the electric switch and to control a gate signal of the electric switch depending on the current change; a gate buffer; and at least one current source, arranged to drive the gate buffer. The current change rate sensor is connected to control the current source to thereby control the gate signal of the electric switch.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.

Abstract: The invention concerns a method for controlling a switching assembly comprising a plurality of transistors connected in parallel, having a linear operating mode, a closed-switch operating mode and an off operating mode including a first operating phase during which a current flows from a source terminal to a drain terminal and a second operating phase during which no current flows. The method includes the following successive steps; (a) controlling the switching assembly in closed-switch mode during part of the first phase; (b) controlling the switching assembly in linear mode; (c) controlling the assembly in off mode during part of the second phase.

Abstract: An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched capacitor element being located in a second branch of the bridge circuit. A detector circuit is coupled to the first branch and to the second branch of the bridge circuit. Switching signals of the first switched capacitor element and of the second switched capacitor element are generated on the basis of an input clock signal of the integrated circuit.

Abstract: A System for generating a PWM output voltage signal include a first half bridge having a first set of switches, and a second half bridge having a second set of switches. A control unit is configured to generate a first PWM switch-signal for switching the first set of switches; to generate a second PWM switch-signal for switching the second set of switches; and to vary at least one of pulse widths and phases of the first and second PWM switch-signals relative to each other for varying a pulse width of a PWM output voltage signal so that the PWM output voltage signal equals zero when the pulse widths of the first and second PWM switch-signals are equal to each other.

Abstract: A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power switching devices can also be reduced. The gate drive circuit can clamp and keep the voltage across the gate capacitor to a certain level while the power switching devices turn on, and it can also clamp and keep the voltage across the gate capacitor to almost zero while the power switching devices turn off. The gate drive circuit comprises four small semiconductor bidirectional conducting switching devices connected in full-bridge configuration. An inductor is connected to the two junctions of the full-bridge configuration to help switching the current direction. A capacitor in series with the inductor is necessary for some applications.

Abstract: A resonate gate drive circuit for driving at least one power switching device recovers energy loss for charging and discharging the gate capacitance of the power switching devices. The gate drive circuit uses a current source to charge and discharge the gate capacitance with a high current, reducing the switching loss of the power switching device. The gate drive circuit comprises four semiconductor bidirectional conducting switching devices connected in a full-bridge configuration. An inductor connected across the bridge configuration provides the current source. The gate drive circuit may be used in single and dual high-side and low-side, symmetrical or complementary, power converter gate drive applications.

Abstract: A voltage/current (V/I) source includes circuitry having first, second, third and fourth nodes, a first current source electrically connected to the first node, a second current source electrically connected to the second node, where the third and fourth nodes are between the first and second nodes, and an operational amplifier (op-amp) having an output, an inverting input, and a non-inverting input. The output is electrically connected to the third node, and the non-inverting input is electrically connected to a voltage source. A feedback line is between the fourth node and the inverting input.

Abstract: A discharge protection circuit for discharging a full-bridge circuit in a brushless DC fan, wherein the brushless DC fan comprises a control circuit outputting at least one first control signal and at least one second control signal to the full-bridge circuit. The second control signal is a reverse signal of the first control signal; and the full-bridge circuit comprises a first impedance, a second impedance and a switch. The switch has a first terminal, a second terminal, and a third terminal that is grounded. The first terminal and the first impedance are in series connection for receiving the first control signal to control the status of the switch. The second terminal and the second impedance are in series connection and are connected to the input terminal of the second control signal of the full-bridge circuit, and the full-bridge circuit is discharged according to the status of the switch.

Abstract: A method and apparatus for optically clocked optoelectronic track and hold (“OCOETH”) device. The OCOETH device includes a diode bridge, input node, at least two current sources and at least two photodetectors. The input node is operatively coupled to the diode bridge and can receive an analog input signal. The at least two current sources are operatively coupled to the diode bridge and can forward bias the diode bridge. The at least two photodetectors are operatively coupled to the diode bridge and can receive an optical input clocking signal, and can reverse bias and forward bias the diode bridge in response to the optical input clocking signal. The hold capacitor is operatively coupled to the diode bridge and can track the analog input signal when the diode bridge is forward biased, and can hold the analog input signal when the diode bridge switches from forward biased to reverse biased.

Abstract: A circuit for preventing shoot-through in a high side switching transistor coupled in series with a low side switching transistor across a supply voltage, the circuit comprising a voltage reference circuit having an output providing a reference voltage which is negative with respect to the supply voltage provided to the high side switching transistor, the reference voltage being applied to the control electrode of the high side switching transistor when the high side switching transistor is off and the source of the high side switching transistor exceeds the reference voltage and the low side switching transistor is on.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: An electronic discharge circuit. The discharge circuit includes a first current source having first current source input and output and a current control circuit having first, second, third, and fourth control contacts. An electronic circuit element of an electronic circuit has first and second element contacts. If first control contact and first current source input are electrically connected, second control contact and first current source output are electrically connected, third control contact and first element contact are electrically connected, and fourth control contact and second element contact are electrically connected, and if the electronic circuit element is electronically charged, current discharging the electronic circuit element is limited to the current from the first current source, otherwise when so connected, current discharging the electronic circuit element is zero and current from the first current source flows into the second control contact and out the first control contact.

Abstract: A pulse-width modulation circuit converts an input signal into a pulse signal to be supplied to a switch amplifying circuit. The modulation circuit includes a comparison signal generator, an amplitude controller for modulating a comparison signal from the signal generator, and a comparator for comparing the modulated comparison signal and the input signal. The comparator outputs a signal whose level is inverted in accordance with the level of the input signal. The signal outputted from the comparator is supplied to the switch amplifying circuit.

Abstract: A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DCl . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DAl . . . DAj and DBl . . .

Abstract: An H-bridge driver has a drive signal generating circuit for generating a square-wave signal as a drive signal. The H-bridge driver also has a waveform shaping circuit for blunting the waveform of the drive signal at the rising and trailing edges thereof. The waveform shaping circuit has a first circuit for generating, in a rising period of the square-wave signal fed thereto, a first current having a positive peak at the center of the rising period, a second circuit for generating, in a trailing period of the square-wave signal fed thereto, a second current having a negative peak at the center of the trailing period, and a capacitor to which the first and second currents are fed. The waveform shaping circuit outputs the voltage across the capacitor as its output voltage.

Abstract: In a high frequency switch, first and second diodes are respectively connected between first and second ports and between first and third ports so that they are directed in the same direction with respect to the first port. Coupling capacitors are connected on both sides of the respective diodes. Distributed constant lines and capacitors are connected between points of connection between the respective diodes and the corresponding capacitors, and reference potentials. Control voltage terminals are connected to points of connection between the distributed constant lines and the capacitors. A distributed constant line and a capacitor are connected between the first port and a reference potential. A fixed voltage terminal is connected through a resistor to a point of connection between the distributed constant line and the capacitor.

Abstract: This invention provides a method and apparatus for magnetic amplifier to reduce the minimum load requirement of power supply. The apparatus comprises a voltage-dropper and a current-limiter. Through the voltage-dropper and the current-limiter, the master output of the power supply is coupled to the output of magnetic amplifier. The differential voltage of the master output and the magnetic amplifier output decide the voltage of the voltage-dropper. The current-limiter limits the current flows from the master output to magnetic amplifier output. If the master output is no load and the magnetic amplifier is full load condition, a start-up current will flow from the master output to the output of magnetic amplifier via the voltage-dropper and the current-limiter. In the mean time, the start-up current will widen the pulse width of the PWM signal until the current-limiter limits the current. The maximum current of the current-limiter is assigned to maintain the minimum pulse width of the PWM signal.

Abstract: In an overcharge prevention method for a voltage storage element connected to a bridge rectifier circuit which includes a first switching section connected between one input terminal supplied with an AC voltage and a first power source line, a second switching section connected between the other input terminal supplied with the AC voltage and the first power source line, a third switching section connected between the one input terminal and a second power source line, and a fourth switching section connected between the other input terminal and the second power source line, both the first and second switching sections or both the third and fourth switching sections are concurrently turned on, forming a closed loop path between the one input terminal and the other input terminal, and thus the charge voltage at the voltage storage element is prevented from exceeding a withstand voltage of the voltage storage element, and the overcharging of the voltage storage element is avoided.

Abstract: A temperature-compensated diode rectifier circuit is coupled to the outside of an HF amplifier (PA) to derive a rectified voltage (UD) from an HF output signal (RFOUT) with a rectifier input (IR) via a directional coupler (D-CO) with secondary connections (1, 2), and has a rectifier output (OR) for the rectified voltage (UD), a rectifier diode (D1), a charging capacitor (C1) and a ballast resistor (R2). To stabilize the rectified voltage against temperature influences, the rectifier input (IR) is connected to a d.c. input voltage (UIN), and a compensating diode (D2) is in series with the ballast resistor (R2), and a dropping resistor (R1) is in series with the rectifier diode (D1). According to the invention the rectifier diode (D1), the compensating diode (D2), the dropping resistor (R1), the ballast resistor (R2) and the directional coupler (D-CO) are connected to the d.c. input voltage (UIN) so that the voltage amplitude of the decoupled HF output signal (RFOUT) is added to the d.c. input voltage (UIN).

Abstract: An active damping circuit damps the ringing effect caused by a write circuit for a disk drive. The circuit includes upper switches and lower switched current sources. A capacitive feedback is connected between the output and the lower switched current sources.

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract: A programmable load circuit operable to generate a plurality of test signals is described. The programmable load circuit comprises a diode bridge coupled between an input and an output. The diode bridge compares the voltage on the input to the voltage on the output. The programmable load circuit also comprises a plurality of current sources. A first set of the plurality of current sources are coupled to intermediate nodes of the diode bridge. Additionally, the programmable load circuit comprises a switching circuit coupled between the intermediate nodes of the diode bridge and a second set of the plurality of current sources. Furthermore, the programmable load circuit also comprises a load regulator coupled to the output and the intermediate nodes of the diode bridge. The load regulator is configured to reduce leakage current on the output.

Abstract: An array of electrical elements is arranged in rows and columns, signals being read out from the column conductors. Each column has a multiplexer switch so that signals from a number of columns may be switched to a common output. Each multiplexer switch comprises a diode bridge (36-39) having an input (60) and an output (34). Current is supplied to the diode bridge through a supply diode (52) and drained from the bridge through a drain diode (54), for controlling the switching of the bridge. The all-diode switch may be integrated on the substrate of the array and has a substantially linear switching response.

Abstract: A large-area electronic device comprises an array (1) of device elements (2,3) coupled to row and column conductors (A and B). The column conductors (B) are arranged in groups, (e.g M, M+1, M+2), and a column multiplexer circuit (C) couples the column conductors (B) of a respective group to a respective common terminal (5). The present invention provides a compatible multiplexer circuit (C) for the array (1), the operation of the circuit (C) using electrical switching rather than optical switching. This multiplexer circuit (C) for each column conductor comprises a diode bridge (SD3 to SD6) and may include a clamping switch (SD1, SD2). A signal is transmitted between the column conductor (B) and a common output terminal (5) in a first state of the diode bridge (SD3 to SD6). The potential of the column conductor (B) is clamped by the clamping switch (SD1, SD2) in a second state of the diode bridge.

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (V.sub.DD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).

Abstract: A driver circuit for a semiconductor test system generates test signals having predetermined voltage levels without being affected by stray capacitances.

Abstract: A multi-level driver circuit comprises: (a) an output buffer; (b) a first switch for applying a first analog level to the output buffer when in a closed state; (c) a second switch for applying a second analog level to the output buffer when in a closed state; (d) a third switch for applying a third analog level to the output buffer when in a closed state, wherein the third switch applies to the output buffer a capacitance which is dependent upon level when the third switch is in an open state and is unclamped; and (e) a clamping circuit for clamping the third switch such that the third switch applies to the output buffer a capacitance which is substantially independent of the third analog level when the third switch is in an open state and is clamped by the clamping circuit. The switches can be solid-state switches, such as diode bridges. Any number of switches can be provided, and more than one of the switches can be provided with a clamping circuit.