Abstract: A bipolar junction transistor (BJT) used as a synchronous rectifier (SR) that is turned off by an active electronic device such as a transistor coupled between the base and collector of that SR BJT. The turn-off transistor functions to rapidly remove stored charge from the collector-base junction of the SR BJT when appropriate. Various active electronic devices are discussed as implementations of the turn-off transistor, including bipolar and field effect transistors of same or opposite polarity. Various anti-saturation and base current increasing circuits are also disclosed.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A sample-and-hold circuit is coupled to the input terminal, the inverted input terminal, the clock terminal, and the inverted clock terminal. A comparator circuit is coupled to the sample-and-hold circuit, the clock terminal, and the inverted clock terminal. A latch circuit is coupled to the comparator circuit, the clock terminal, and the inverted clock terminal. An output terminal having a quantized output signal is coupled to the latch circuit. An inverted output terminal having an inverted output signal is coupled to the latch circuit.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: A first partial circuit is formed by grounding the emitter electrode of a first negative differential resistive element, connecting the emitter electrode of a second negative differential resistive element to the collector electrode of the first negative differential resistive element, and connecting a first field-effect transistor in parallel with the first negative differential resistive element. A second partial circuit is formed by grounding the emitter electrode of a third negative differential resistive element, connecting the emitter electrode of a fourth negative differential resistive element to the collector electrode of the third negative differential resistive element, and connecting a second field-effect transistor in parallel with the third negative differential resistive element. An output from the first partial circuit is input to the input of the second partial circuit. The inversion of the output of the second partial circuit is input to the input of the first partial circuit.

Abstract: In an MOS type power switching device, no leak current flows during an OFF-state, and a high current driveability is realized during a normal load condition. Furthermore, a drive current is reduced during a short-circuited load condition.