Abstract: Provided is a photoelectric conversion device including: a pixel including a plurality of photoelectric conversion units; and a select unit configured to control each of the plurality of photoelectric conversion units to be in an active state or an inactive state. The plurality of photoelectric conversion units has a first group including a first avalanche diode and a second group including a second avalanche diode. The select unit controls the second group to be in the inactive state in a first case of controlling the first group to be in the active state, and the select unit controls the first group to be in the inactive state in a second case of controlling the second group to be in the active state. The pixel has no photoelectric conversion unit which is in the active state in both the first case and the second case.

Abstract: Various methods and circuital arrangements for complete turn OFF of branches of a multi-branch cascode amplifier are presented. According to one aspect, a protection circuit coupled to a source node of an output transistor of a branch couples a reference voltage to the source node of the output transistor when the branch is turned OFF, and decouples the reference voltage from the source node when the branch is turned ON. According to another aspect, the protection circuit includes a switch whose off capacitance is sufficiently low so as not to affect performance of the branch when the branch is ON, and whose on resistance is sufficiently low to sufficiently reduce an RF amplitude at the source node of the output transistor when the branch is OFF and other branches are ON, and therefore allow use of low-voltage thin-oxide transistors in the branch. Further aspects include a second switch and use of transistor switches.

Abstract: A solar cell assembly (200) is presented. The solar cell assembly includes one or more solar cell units (21 1) coupled in series. The solar cell unit includes a first solar cell series (221) and a second solar cell series (222) connected in parallel. The first and second solar cell series include a plurality of cells (202) connecting in series respectively. The solar cell assembly also includes a by-pass diode (201) coupled to each solar cell unit and shared between the first and second solar cell series in each solar cell unit.

Abstract: A solar cell assembly (200) is presented. The solar cell assembly includes one or more solar cell units (21 1) coupled in series. The solar cell unit includes a first solar cell series (221) and a second solar cell series (222) connected in parallel. The first and second solar cell series include a plurality of cells (202) connecting in series respectively. The solar cell assembly also includes a by-pass diode (201) coupled to each solar cell unit and shared between the first and second solar cell series in each solar cell unit.

Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.

Abstract: A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit.

Abstract: A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit.

Abstract: Low leakage diodes and methods of forming the same are disclosed. In one embodiment an apparatus includes a designed or parasitic bipolar transistor having an emitter, a base and a collector. The bipolar transistor is configured to operate as a diode, the diode having reverse-biased and forward-biased modes of operation. The emitter and base operate as first and second terminals of the diode, respectively. The collector is configured to receive a collector bias voltage, which is controlled relative to a voltage of the emitter to reduce a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.

Abstract: A junction box electronically connected to a solar panel and connected to a plurality of solar cell strings connected in series includes a first bypass diode string and at least one second bypass diode. The first bypass diode string includes a plurality of first bypass diodes forwardly connected in series, and each of the plurality of first bypass diodes is connected to a corresponding one of the plurality of solar cell strings in parallel. The at least one second bypass diode connected to at least two neighboring solar cell strings in parallel, turns on to bypass the at least two neighboring solar cell strings upon the condition that the at least two neighboring solar cell strings are abnormal simultaneously.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D1/D2, D3/D4) are connected to each other in a mirrored configuration to obtain a basic switching cell. This basic switching cell can be used to build a SPDT switch which in turn can be used to build a DPDT switch or switches of higher complexity. Thereby, high isolation and low power consumption can be achieved with the additional advantage of modularity.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DCl . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DAl . . . DAj and DBl . . .

Abstract: A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage value, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby preventing the occurrence of the electromagnetic noise and an excessively large voltage.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A circuit for active decoupling of transmit coils in Nuclear Magnetic Resonance imaging apparatuses, particularly of the low field type, includes at least one PIN diode (D1), which is connected in series with the conductors of at least one transmit coil (1) and has at least one input (4) for an incoming bias current. The circuit has at least one additional diode (D2) which is a silicon diode connected in antiparallel with the PIN diode (D1).

Abstract: A signal switching circuit has first to fourth diode pairs each comprising two series-connected diodes disposed respectively between a first input terminal and a first output terminal, between a second input terminal and the first output terminal, between the first input terminal and the second output terminal, and between the second input terminal and the second output terminal, and first to fourth capacitor circuits connected respectively between diode-to-diode connection points in the diode pairs and the ground. The first or second diode pair is rendered conductive in an alternative manner. Likewise, the third or fourth diode pair is rendered conductive in an alternative manner. A low pass filter for passing therethrough the corresponding first or second signal uses residual inductance in each of the diode pairs thus rendered conductive and the associated capacitor circuit.

Abstract: A high frequency switch, has

Abstract: Input/output circuitry for electrically protecting an internal element includes an input/output terminal connected to the internal element, a pair of first and second power terminals applied with a bias voltage, a series connection of a diode and a bipolar transistor between the pair of first and second power terminals so that an intermediate point between the diode and the bipolar transistor is connected to the input terminal, and a parasitic resistance connected between a base of the bipolar transistor and the diode so that the diode is connected between the parasitic resistance and an emitter of the bipolar transistor. An electrostatic pulse applied to the input/output terminal is clamped by the series connection of the diode and the bipolar transistor to protect the internal element from an electrostatic pulse applied to the input/output terminal.

Abstract: A voltage level converter having: an input bias terminal; connect to first, second and third voltage sources; first and second complementary output terminals; and an input control terminal wherein, said input bias terminal is connected to a third output terminal of an automatic bias stage, said bias stage having connections to said voltage sources for providing substantially said first low voltage to said third output terminal in the absence of said second high voltage and providing a third voltage that is greater than said first low voltage when said second high voltage is present, said third voltage being derived from said second high voltage.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: An output circuit is provided for obtaining an output signal at one of two voltages regardless of the relative difference between the voltage levels. The output circuit includes a first switching circuit that contains two current sources for selectively producing one of two constant currents. A second switching circuit receives one of the two constant currents. The first and second switches are connected by four series-connected forward biased diodes. There are also bypass connectors for selectively providing current around the first and fourth diodes. An output terminal is located between the second and third diodes. A high voltage source is located between the first switching circuit and the first diode. A low voltage source is located between the fourth diode and the second switching circuit. Depending which of the current sources are actuated, the signal present at the output terminal is either that of the high voltage source or that of the low voltage source.

Abstract: A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.