Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: In a gate drive circuit of which an N-channel MOSFET and a P-channel MOSFET are connected in a push-pull manner to amplify an input pulse signal and drive an output element, a temperature correction circuit is connected between gate terminals of the N-channel MOSFET and the P-channel MOSFET. The temperature correction circuit lowers each of gate voltages of the N-channel MOSFET and the P-channel MOSFET as ambient temperature rises.

Abstract: An embodiment relates to a method of measuring an ambient temperature by using a temperature sensor provided in an integrated circuit (IC) and a measurement error of a temperature sensor may be improved by correcting an output value of a temperature sensor by using a correction value stored in a memory.

Abstract: A control system for use in a power converter having a plurality of outputs comprising a primary switching control block, a secondary control block, and a multi-output control block. The primary switching control block is coupled to control switching of a primary switch. The secondary control block is coupled to control switching of a synchronous rectifier switch. The multi-output control block is coupled to control switching of at least one pulse transfer switch coupled to one of the plurality of outputs. A request for an energy pulse is transferred to the primary switching control block to turn ON the primary switch to transfer the energy pulse to one of the plurality of outputs. The multi-output control block comprises an interface to send the request for the energy pulse and to receive an acknowledge signal to and from the secondary control block.

Abstract: Pressure sensors that can be reliability operated with the maximum current flowing through the device restricted to 10 uA or below, or below 50 uA in a single-fault condition. This can provide at least a reduced need for the final medical device architect to consider potential risks from excessive current to the patient, simplifying the design and manufacturability of the medical device. An additional benefit is that the sensors are generally more accurate at lower current flow, as self-heating of the resistors and parasitic leakages are reduced, if the signal-to-noise problem is resolved.

Abstract: A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

Abstract: A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and/or receiving temperature information.

Abstract: The present invention describes a method of accelerating execution of one or more application tasks in a computing device using machine learning (ML) based model. According to one embodiment, a neural accelerating engine present in the computing device receives a ML input task for execution on the computing device from a user. The neural accelerating engine further retrieves a trained ML model and a corresponding optimal configuration file based on the received ML input task. Also, the current performance status of the computing device for executing the ML input task is obtained. Then, the neural accelerating engine dynamically schedules and dispatches parts of the ML input task to one or more processing units in the computing device for execution based on the retrieved optimal configuration file and the obtained current performance status of the computing device.

Abstract: The present disclosure provides a Multiple Inputs Multiple Outputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

Abstract: A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.

Abstract: An electronic device includes a precision reference circuit, which contains a bandgap reference circuit and an offset-correction circuit. The bandgap reference circuit has an output that is coupled to provide a bandgap reference voltage and an intermediate node that is separated from the output by a transimpedance resistor. The offset-correction circuit is coupled to the bandgap reference circuit and includes a DAC. The DAC is coupled to the intermediate node and is also coupled to receive an external digital value. The external digital value determines a fraction of a correction current that will be passed by the DAC.

Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a reference voltage generator, which includes a first candidate circuit configured to generate a first candidate reference voltage, a second candidate circuit configured to generate a second candidate reference voltage, and a selector circuit configured to select one of the first and second candidate reference voltages. The reference voltage generator also includes a third circuit configured to generate a power supply voltage based on the selected candidate reference voltage.

Abstract: A RF switching arrangement (400) is described including a bias swap circuit (30). The bias swap circuit switches the bias voltage dependent on the state of the RF switch. This improves the performance of the RF switch without requiring charge pump circuitry.

Abstract: Described herein are methods and systems for configuring sensors to compensate for a temperature gradient. Multiple sensor sets, each having at least two sensors of a same type with orthogonal axes, are positioned to form at least one opposing sensor pair, in which an axis of one sensor of one sensor set is in an opposite orientation to an axis of one sensor of another sensor set. A combined measurement of each opposing sensor pair may be output which is compensated for an effect of a temperature gradient on sensor measurements of the sensors.

Abstract: A temperature controlled enclosure that includes a temperature control device for controlling the temperature within an internal cavity of the temperature controlled enclosure. The temperature controlled enclosure also includes one or more charging ports for receiving and charging a battery pack. A controller within the temperature controlled enclosure controls the temperature within the internal cavity to a predetermined or desired temperature (e.g., 20° C.). When a battery pack is received in the one or more charging ports, the temperature of the battery pack can be determined. If, for example, the temperature of the battery pack is below 0° C., the battery pack is allowed to warm up inside the temperature controlled enclosure before the battery pack is charged.

Abstract: An antenna device includes an antenna unit that receives radio waves of a plurality of first frequency bands and outputs received signals, and a first band pass filter that transmits, out of the received signals that are output, received signals of at least two second frequency bands out of the first frequency bands.

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

Abstract: A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.

Abstract: A power control circuit includes: a voltage-current converter and a programmable current amplifier; the voltage-current converter is configured to detect an inputted output power control signal, and to convert the output power control signal to a control current and output same; and the programmable current amplifier is configured to receive the control current and output the amplified control current as a bias current of the power amplifier connected to the power control circuit.

Abstract: An embodiment for an integrated circuit for temperature detection includes: a closed loop circuit branch including: a first bipolar junction transistor (BJT), a first resistor coupled between a first base of the first BJT and a junction node, and an amplifier having an output coupled to the junction node and a non-inverting input coupled to a collector of the first BJT; and an open loop circuit branch including: a second BJT, a second resistor coupled between a base of the second BJT and the junction node, a third resistor coupled between the base of the second BJT and ground, and a comparator having an inverting input coupled to a collector of the second BJT and an output configured to provide a digital voltage signal that corresponds to a temperature reading.

Abstract: In accordance with an embodiment, a device includes an interface configured for obtaining at least one measurement signal from a temperature sensor. In a first time interval the at least one measurement signal comprises information about a temperature-dependent voltage difference between a first temperature-dependent voltage at a first diode of the temperature sensor and a second temperature-dependent voltage at a second diode of the temperature sensor. In a second time interval the at least one measurement signal comprises information about a measurement value of a temperature-dependent voltage at a temperature-dependent electrical component of the temperature sensor.

Abstract: A processing system comprises sensor circuitry and a baseline correction mechanism. The sensor circuitry comprises a receiver channel having an input configured to acquire a resulting signal from a sensor electrode. A background capacitance is formed between the sensor electrode and a conductive element. The baseline correction mechanism is coupled to the input of the receiver channel. The baseline correction mechanism comprises a resistive element configured to be driven with a compensation signal to at least partially mitigate the background capacitance.

Abstract: Provided is a graphics processing unit and an operation method thereof. The graphics processing unit includes a plurality of cores in which a delay time between an input and an output decreases according to an increase of a temperature, a temperature monitoring and sorting circuit configured to monitor a temperature of each of the plurality of cores, and a controller configured to control a clock frequency and a power supply of the plurality of cores based on a drivable clock frequency of a core having the lowest temperature among temperatures of each of the plurality of monitored cores.

Abstract: An electronic device is disclosed. The electronic device includes a case and a battery cover forming an appearance of the electronic device and a printed circuit board mounted inside the case and provided with electronic elements. A measurement sensor is mounted on at least a portion of the printed circuit board. One surface of a recess of the printed circuit board, on which the measurement sensor is mounted, is formed at a different height from other portion of the printed circuit board in a thickness direction of the electronic device. The recess, on which the measurement sensor is mounted, is thinner than the other portion and is spaced apart from the other portion, and thus the electronic device can more accurately measure a body temperature of a user.

Abstract: A temperature detection device which receives a temperature signal from a temperature sensor and outputs an electrical signal corresponding to the temperature signal. A temperature slope which is an amount of change in an output of the electric signal relative to an amount of change in the temperature signal is changed at a predetermined temperature threshold.

Abstract: A time domain temperature sensor circuit includes a voltage generating circuit configured to generate and equalize a first voltage of a first node and a second voltage of a second node, a current generating circuit comprising a first semiconductor device connected between the first node and a ground, and configured to generate a first current, and a variable resistor circuit and a second semiconductor device connected in series between the second node and the ground, and configured to generate a second current, the variable resistor circuit being configured to vary a temperature gradient of the second current based on resistance variations by the variable resistor circuit, and a current mirror circuit configured to generate a third current by performing current mirroring of the second current and transmit the third current to an output terminal.

Abstract: Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2). The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.

Abstract: A common mode voltage level shifting and locking circuit is provided. The common mode voltage level shifting and locking circuit includes an operational amplifier, a source follower, a first feedback circuit, and a second feedback circuit. The operational amplifier generates a first common mode voltage. The source follower shifts the first common mode voltage to generate a second common mode voltage. The first feedback circuit generates a first control signal according to the second common mode voltage. The operational amplifier adjusts the first common mode voltage according to the first control signal. The second feedback circuit generates a second control signal according to an external reference voltage provided by a next stage circuit. The source follower adjusts the second common mode voltage according to the second control signal such that the next stage circuit reaches a maximum input common mode range.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: A circuit includes: a first node to receive a first current; a first resistive element receiving a first branch current of the first current; first transistors each including a first terminal connected to the second end of the first resistive element; a second resistive element connected to the first node and receiving a second branch current of the first current; a second node to receive a second current; a second transistor including a first terminal, the first terminal of the second transistor connected to the second node and receiving a first branch current of the second current; a third resistive element connected to the second node and receiving a second branch current of the second current; wherein a temperature coefficient is adjusted by a resistance of the second resistive element and a resistance of the third resistive element and corresponding to the first current.

Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slop value represents a change of a read voltage level as a function of a write-to-read delay time of a memory sub-system. In response to a read command, a current write-to-read delay time and a current die temperature are determined. Using the data structure, a stored slope value corresponding to the current die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value and the current write-to-read delay time. The read command is executed using the adjusted read voltage level.

Abstract: An optoelectronic device including a support having a rear surface and a front surface opposite each other, a plurality of nucleation conductive strips forming first polarization electrodes, an intermediate insulating layer covering the nucleation conductive strips, a plurality of diodes, each of which having a first, three-dimensional doped region and a second doped region, and a plurality of top conductive strips forming second polarization electrodes and resting on the intermediate insulating layer, each top conductive strip being disposed in such a way as to be in contact with the second doped regions of a set of diodes of which the first doped regions are in contact with different nucleation conductive strips.

Abstract: The present disclosure provides an optical sensor having constant sensitivity regardless of changes in temperature. The optical sensor may include a light emitting device configured to emit light; a light receiving device configured to receive the light emitted from the light emitting device, and to output current based on an intensity of the light; a temperature sensor coupled with the light emitting device, and having electrical resistance varying with temperature; and a microcontroller including a first channel for supplying first current directly to the light emitting device, a second channel for supplying second current to the light emitting device via the temperature sensor, and a third channel for receiving the current output from the light receiving device.

Abstract: A power supply is disclosed. The power supply includes a switching converter for providing an output voltage comprising a power switch coupled to a driver for driving the power switch with an on-off switching cycle; and a voltage threshold indicator. The voltage threshold indicator includes an input for receiving an output of the converter, and an output coupled to the driver. The voltage threshold indicator is adapted to provide a temperature compensated voltage threshold, and a control signal to control the on-off switching cycle. The control signal is adapted such that when the output voltage exceeds the temperature compensated voltage threshold, a value of the control signal changes.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a first circuit, an analog-to-digital converter, an external input terminal, a selector, and a second circuit. The first circuit is configured to generate a first voltage corresponding to a temperature. The analog-to-digital converter is configured to convert the first voltage into a first digital value. The external input terminal is a terminal to which a second digital value is input from outside. The selector is configured to select either the first digital value or the second digital value. The second circuit is configured to generate a second voltage based on a third digital value being a digital value selected by the selector.

Abstract: A power circuit applied to an electronic device, includes: a control circuit and a power providing circuit, wherein the control circuit is coupled to at least one circuit installed within the electronic device, and is arranged to generate a providing information according to at least one performance indicator of the circuit, wherein the providing information includes an optimal voltage signal setting, and the optimal voltage signal setting is generated according to a performance coefficient corresponding to each performance indicator; the power providing circuit is coupled to the control circuit and the at least one circuit, and is arranged to dynamically provide a voltage signal to the circuit according to the providing information.

Abstract: A reference voltage generator circuit (100) is disclosed, comprising a first transistor (101) having a first channel type and a second transistor (102) having a second channel type. A current source (104) is connected to a source terminal of the first transistor (101). A drain terminal of the second transistor (102) is connected to a drain terminal of the first transistor (101). The reference voltage generator circuit (100) further comprises a third transistor (103) having the second channel type, wherein a drain terminal of the third transistor (103) is connected to a source terminal of the second transistor (102). A node between the source terminal of the second transistor (102) and the drain terminal of the third transistor (103) is connected to a gate terminal of the first transistor (101). A connection for a reference voltage (Vrc) is provided between the current source (104) and the source terminal of the first transistor (101).

Abstract: Materials and methods for improving the DC and RF performance of off-state step-stressed high electron mobility transistors (HEMTs) and devices are provided. A semiconductor device can include at least one HEMT and an on-chip heating source. A method of recovering the DC and RF performance of a stressed semiconductor device can include annealing the device with a built-in heating source of the device.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a first integrated circuit (IC) and a second IC. The direction pin of the first IC outputs a direction control signal to the direction pin of the second IC. The first IC takes a control right when the direction control signal is in a first logic state. The clock pin of the first IC outputs a first clock signal to the clock pin of the second IC when the first IC takes the control right. The second IC takes the control right when the direction control signal is in a second logic state. The clock pin of the second IC outputs a second clock signal to the clock pin of the first IC when the second IC takes the control right.

Abstract: An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

Abstract: A modular control apparatus, having a head module, and at least one supply module and peripheral module arranged on the head module and having a bus structure. The supply module and the peripheral module have a base module part, an electronic module part and a connection module part. The base module parts are arranged next to one another and provide the bus structure that electrically couples the head module, the supply module and the peripheral module to one another. The supply module additionally comprises an electrical line that runs from the connection module part through the electronic module part to the base module part and connects the supply connection of the supply module to the bus structure. An overload identification unit is arranged at the electrical line and determines a parameter of the electrical line and produces a warning signal if the parameter exceeds a threshold value.

Abstract: An insulated gate semiconductor device includes a main insulated gate transistor having a gate electrode controlling a main current, a current-detecting insulated gate transistor, which is disposed in parallel to a main insulated gate transistor, outputting a current on a proportional basis in size between the transistors to the main current flowing through the main insulated gate transistor, a temperature detecting diode formed integrally with these insulated gate transistors in a semiconductor substrate. Interposing an ESD tolerance Zener diode between an emitter electrode of the current-detecting insulated gate transistor and an anode electrode of the temperature detecting diode leads to securing the ESD tolerance for the current-detecting insulated gate transistor by using the temperature detecting diode.

Abstract: An IGBT temperature sense circuit is provided. The IGBT temperature sense circuit automatically calibrates a temperature sense of a diode to minimize an error based on element characteristics of a temperature sense diode, precisely senses the temperature and removes a limit of a maximum current (to increase the maximum current) of an output of an IGBT. A temperature sense circuit includes an automatic calibrator that is configured to supply current of a current source to a current to a diode and a diode temperature sensor that is configured to measure a voltage of one side terminal of the diode based on the current of the diode based on a change of a temperature and adjustment of an operation of a protection object device.

Abstract: This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.

Abstract: A temperature-compensated rectifying component is configured to receive an input signal and comprises: a diode part, for rectifying the received input signal and providing a rectified output signal thereby, the diode part having an operational temperature; and a temperature compensation controller, configured to control a power dissipated by the diode part over a predetermined period of time, such that an average of the operational temperature over the predetermined period of time meets pre-set criteria. This may be used in a RF detector for generating a DC level from a RF input signal, which may form part of a control circuit for setting an amplitude of an RF potential for supplying to an electronic amplifier in an analytical instrument, such as an ion optical device.