Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: A patch panel includes a connector, a first switch circuit, a number of output circuits, a number of output terminals, and a complex programmable logic device (CPLD). The CPLD is capable of receiving a control signal from a controller via the connector, and sending the control signal to one of the output terminals via the first switch circuit, for signaling the controller to communicate to a peripheral device connected to the output terminal.

Abstract: A semiconductor device has: a pull-up circuit connectable to an internal terminal; a pull-down circuit connectable to the internal terminal; and an operation mode switch circuit. The operation mode switch circuit switches an operation mode based on a potential of the internal terminal when the pull-up circuit is connected to the internal terminal and a potential of the internal terminal when the pull-down circuit is connected to the internal terminal.

Abstract: A temperature control device for controlling temperature of semiconductor device. The temperature control device comprising, a leak current detection unit for detecting leak current of the semiconductor device, and a temperature control unit for controlling temperature of the semiconductor device so that the leak current is within predetermined current range, if the leak current exceed the predetermined current range.

Abstract: An embodiment of the invention relates to an apparatus including a power semiconductor device and a processor coupled thereto. The processor is configured to provide a control signal to the power semiconductor device to regulate an output characteristic of the apparatus. The processor models an internal characteristic of the power semiconductor device and alters the control signal if the modeled internal characteristic crosses a threshold value. In an exemplary embodiment, the internal characteristic is a channel temperature of a MOSFET. A sensor such as a thermistor is coupled to or included within the processor to sense a parameter separate from the power semiconductor device, such as a processor temperature, and the processor is configured to adapt the modeled internal characteristic to the sensed parameter.

Abstract: A plug adapter in combination with a pre-set digital timer (in minutes) that plugs into an electrical wall outlet and safely disconnects the current to any device plugged into the adapter after a pre-set time period has elapsed. The pre-set timer and plug adapter includes an on-off push button switch and a selector button to choose a shorter time period as desired.

Abstract: The present invention discloses a power driving device for an electronic device, comprising: a data input terminal capable of receiving a sequential data comprising at least a first power control sequential data and at least a second power control sequential data; an operation module capable of performing operation on the first power control sequential data and the second power control sequential data to generate a control signal; and a power control module coupled to the operation module to generate at least an output power according to the control signal. Therefore, the control signal can be used to control various power states of an electronic device.

Abstract: A control circuit for controlling a motor. The control circuit includes a control module, a current transformation module and a comparison module. The control module generates a control current and a comparison voltage according to a first current, a first voltage and an input voltage. The current transformation module, coupled to the control module, generates a first output voltage from a first output terminal and a second output voltage from a second output terminal. The comparison module, coupled to the control module and the current transformation module, compares a threshold voltage, the first output voltage, the second output voltage, and the comparison voltage and generates a plurality of control signals to control the motor.

Abstract: Inspection systems, circuits, and methods are provided to enhance defect detection by reducing thermal damage to large particles by dynamically altering the incident laser beam power level supplied to the specimen during a surface inspection scan. In one embodiment, an inspection system includes an illumination subsystem for directing light to a specimen at a first power level, a detection subsystem for detecting light scattered from the specimen, and a power attenuator subsystem for dynamically altering the power level directed to the specimen based on the scattered light detected from the specimen. For example, the power attenuator subsystem may reduce the directed light to a second power level, which is lower than the first, if the detected scattered light exceeds a predetermined threshold level. In addition reducing thermal damage, the systems and methods described herein may be used to extend the measurement detection range of an inspection system by providing a variable-power inspection system.

Abstract: Systems and methods are provided for automatically driving and maintaining oscillation of an assembly system including a mass and a bias member (which may also be referred to as a spring or elastomeric member) at or near a resonant frequency of the assembly system. In one example, apparatus for maintaining oscillation of a moveable subassembly including a mass and a bias comprises a controller operable to receive a signal from a sensor associated with a position or motion of the subassembly, and generate a drive signal for driving the subassembly in response to the received signal from the sensor. In this manner, the controller may monitor the motion of the subassembly and adjust or modulate the driving force over time to maintain the subassembly at or near a resonant frequency. Further, in one example, the subassembly includes a resonant engine comprising a movable mirror of an illumination device.

Abstract: A sensor to controller connection system including a power source, a controller in communication with the power source, and a sensor in communication with the power source and the controller, the sensor including sensor electronics and a current source, the current source having a control input and an output, the control input being applied by the sensor electronics and the output being applied to the controller, wherein the current source controls an electric signal communicated to the controller from the sensor based upon the control input.

Abstract: Apparatuses and systems enable power transfer from one or more energy sources to one or more loads. The input power from the energy sources may be unregulated, and the output power to the loads is managed. The power transfer is based on a dynamic implementation of Jacobi's Law (also known as the Maximum Power Theorem). In some embodiments, the energy sources are selectively coupled and decoupled from the power transfer circuitry. In some embodiments, the loads are selectively coupled and decoupled from the power transfer circuitry. Power transfer to the loads is dynamically controlled.

Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.

Abstract: A control circuit for controlling an LED device according to an input data signal and a clock signal is disclosed. The control circuit includes at least one first control module. The first control module includes a shift register unit, a latch register unit, an LED driving circuit, and a latch signal generator. The shift register unit includes at least one shift register and is triggered by the clock signal for buffering data transmitted in the input data signal. The latch register unit includes at least one latch register and is triggered by a latch signal for latching data buffered by the shift register. The LED driving circuit is utilized for driving the LED device according to data latched by the latch register. The latch signal generator is used to generate the latch signal according to the input data signal and the clock signal.

Abstract: A time limiter protects a light emitting diode coupled to an output of a current driver by preventing the light emitting diode from working overtime under a high current and from being overheated and burnt down, no matter whether a pulse width of an input pulse is larger or shorter than a delay time of the time limiter. The input pulse may be a periodic continuous input pulse, or a continuously-enabled pulse generated from a run-time error of software or hardware. The time limiter should be coupled with a discharging circuit for discharging the capacitor in the RC circuit while a periodic continuous input pulse was inputted, to keep the precise original pulse period and pulse width of the enabling signal to be outputted, and to prevent the time limiter from malfunctioning.

Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: Circuit arrangement for controlling the current flow through a load in the case of detection of the current flow according to the current sense principle. The circuit arrangement has a load transistor and a plurality of auxiliary transistors of identical type, which have a control terminal which is connected or can be connected to the control terminal of the load transistor. In the case of the circuit arrangement according to the invention, provision is made of a switching mechanism by which the auxiliary transistors, optionally or depending on the load current or depending on a load path voltage dropped across the load path of the load transistor, can be connected in parallel individually or as a plurality.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: The equivalent circuit is constructed such that a gate terminal is connected to a gate electrode of a P-channel MOS transistor as a varactor and a fixed capacitor is connected between a substrate terminal having a substrate potential and the gate terminal. In addition, source and drain of the P-channel MOS transistor are commonly connected to a source/drain terminal to have the same potential and a first voltage source is connected between the source/drain terminal and the substrate terminal so that the substrate terminal is connected to the positive terminal of the first voltage source. Accordingly, employment of the equivalent circuit of the present invention allows the simulation of the C-V characteristic curve of a voltage-controlled variable capacitive element as an actual device with extremely high accuracy.

Abstract: A CAN controller is equipped with a control circuit that can control whether or not an edge detection signal of a serial signal (CRX input) that is detected by an edge detection circuit is to be input to a re-synchronization circuit causing the execution of a re-synchronizing function prepared in accordance with a CAN protocol. The re-synchronizing function can be made ineffective by inputting into a control signal the control circuit. As a result, the state of synchronization of the CRX input that occurs due to the re-synchronizing function ceases to fluctuate. Therefore, in the CAN controller, a test can be performed with a high speed and stably and without being influenced by the execution of the re-synchronizing function.

Abstract: A current output circuit with two output nodes connectable to a load and providing a plurality of discretely selectable current output magnitudes is provided. The circuit consists of a current driver attached across the output nodes supplying a particular current and one or more bypass resistors connected in parallel with the output nodes that can be switched between a non-conducting state and a resistive conducting state. When a load is connected across said output nodes, the particular magnitude of current sourced through the load can be selected by switching the state of the bypass resistors. The magnitude of the bypass resistors is preselected to provide several discretely selectable states of output current of substantial equal steps. The current driver can be combined with a current switch to increase the number of output states. Several current drivers with current switches may be provided and the bypass resistors integrated into the current switch itself.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: An RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage on the capacitor after a predetermined time has expired since the capacitor began charging up. The result of the comparison, which indicates whether the voltage on the resistor is greater than the voltage on the capacitor, is then used to adjust the capacitance of the capacitor to servo the RC time constant to a predetermined value.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: A computer circuit comprising a driver circuit and a variable loading circuit coupled to the driver circuit. The variable loading circuit is configured to provide a first capacitive load to the output driver while operating according to a first state, and a second capacitive load while operating according to a second state. According to one embodiment, the variable loading circuit includes a first programmable cell element. The variable loading circuit is configured to operate according to the first state in response to the first programmable cell element being programmed. The variable loading circuit is further configured to operate according to the second state in response to the first programmable cell element being erased and a voltage potential being supplied.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programing voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: An electric power dissipation system operates as an active load for power supply testing. The system has a closed loop voltage to current converter with a first and second load terminal. A capacitance is connected across the first and second load terminals. A power supply having a first and second output terminal is coupled to the first and second load terminals via test conductors which have a first and second inductance respectively. A correction signal generator is provided to be responsive to the power supply. The correction signal generator provides an output signal as a function of the voltage generated across one of the inductances. A summing circuit responds to the output signal of the correction signal generator and also responds to a command signal. The output of the summing circuit controls the current flow of the current converter.