Abstract: A low-power op-amp circuit (70) having boosted bandwidth comprises a DC circuit block (72) which is coupled to first (V.sub.DC +, V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes and to an output node (V.sub.OUT) of an output stage (90). The DC circuit block (72) amplifies a differential signal received from the first (V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes, and provides an amplified signal to the output node (V.sub.OUT). An AC circuit block (74) is coupled to the output (NODE 3) of the DC circuit block (72). The AC circuit block (74) is operable to monitor a transient change between the first (V.sub.DC +, V.sub.AC +) and the second (V.sub.DC -, V.sub.AC -) input nodes. The AC circuit block (74) is further operable to transfer charge to the output node (V.sub.OUT) in response to the transient change, thereby providing boosted bandwidth beyond that of the DC circuit block (72) alone.

Abstract: A solid-state switching element that works with at least one semiconductor region or a pair of antiserially arranged semiconductor regions having characteristic curves similar to those of FETs. An internal body diode in inverse operation is also provided. In addition to having a drain and a gate, each of the semiconductor regions has two source electrodes, with several cells combined with the electrodes in cell design. One source serves as a load current electrode, called a load source, and the other source is available as a gate electrode, called a control source. The effective semiconductor region of the load source is larger than the effective semiconductor region of the control source.

Abstract: An amplifier circuit for analog-signal processing has an operational amplifier having an output, an inverting input, and supply inputs for accepting a single supply potential and a reference potential. The operational amplifier has a noninverting input capable of accepting a signal voltage of a varying analog signal input thereto which has a positive value range and a negative value range relative to the reference potential. The output is fed back to the inverting input and the operational amplifier has a differential amplifier having first and second field-effect transistors. The first field-effect transistor has a gate connected to the noninverting input of the operational amplifier and the second field-effect transistor has a gate connected to the inverting input.

Abstract: A differential amplifier circuit includes a differential amplifier having inversion and non-inversion input terminals and input amplifiers each individually connected to one of these input terminals, serving to receive an input voltage within a certain range and output it as another voltage in a smaller range. The differential amplifier is of a kind using n-type and p-type MOS transistors with threshold voltages given respectively by V.sub.thn and V.sub.thp, and connected to a source voltage V.sub.DD and a reference voltage V.sub.ref. Input voltages to the input amplifiers within the range between V.sub.ref and V.sub.DD, are outputted within the range between (V.sub.DD -V.sub.thp) and (V.sub.ref +V.sub.thn), or preferably between (V.sub.DD -1.5V.sub.thp) and (V.sub.ref +1.5V.sub.thn).

Abstract: A two stage operational amplifier circuit comprises a first stage (31) having an input (2, 4) and an output, and a second stage (33) having an input and an output (19). The second stage input is coupled to receive the first stage output. A feedback path (41, 45, 47, 51) is coupled between the output and the input of the second stage. The feedback path (41, 45, 47, 51) comprises a low-frequency compensation path (41, 45) and high-frequency compensation path (45, 47, 51). The feedback path (41, 45, 47, 51) is compensated such that the frequency response of the second output of the second stage is substantially 6 dB per octave throughout the high-frequency region.

Abstract: Apparatus and method utilized in conditioning an input signal from a transducer operatively coupled to a machine by self-biasing a circuit including an op-amp having an inverting signal input terminal, a non-inverting signal input terminal, bias voltage terminals and a signal output terminal. A power supply is operatively coupled to the bias voltage terminals via a single pair of supply lines and an input signal is directed to an input terminal of the op-amp. The op-amp outputs a conditioned signal to the supply lines which is superimposed with said DC bias voltage across the supply lines wherein the characteristics of the conditioned signal may be monitored via the supply lines.

Abstract: An operational amplifier circuit 21 comprises transistors N14, N15 in a first output amplifier circuit 24, and transistors P24, P25 in a second output amplifier circuit 25. When a second differential amplifier circuit 23 is cut off, the output is driven by transistor P13 and transistors N14, N15. When a first differential amplifier circuit 22 is cut off, the output is driven by transistor N23 and transistors P24, P25. Therefore, if such a voltage as to cut off one differential amplifier circuit is given from opposite phase and in-phase input terminals 31, 32, the output can be produced. In such constitution, without using depletion type transistors that require particular manufacturing process, the range of the voltage that can be entered in the input terminal can be extended.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: An RF IC having an improved transconductance comprises a first active device of a first conductance type having a gate, a drain and a source and a second active device of a second conductance type having a gate, a drain and a source. The second active device is coupled in series with the first active device. The gate of the first active device is coupled to the gate of the second active device. A current reuse circuit is coupled to the first active device and the second active device wherein a current flowing from the drain of the first active device is reused in the second active device. Whereby transconductance is increased without an increased current utilization and without an increase in noise.

Abstract: A comparator used in an enhanced N-WELL pad voltage tracking circuit for high (5 Volts) voltage-tolerant buffers is designed to eliminate current leakage when the input/output is tristated and is being driven externally by a weak voltage source. This is accomplished by comparing the pad voltage supplied from the external source to a reference voltage that is a predetermined amount (VTP) less than the low internal voltage source (VDD). Thus, switchover for tracking of the N-WELL voltage tracks very closely the voltage VDD, reducing the differential voltage between the N-WELL and the pad on the pull-up driver for the system, thereby keeping the driver off and eliminating leakage current. The reference voltage is generated either by a diode voltage drop or by a weak source follower.

Abstract: A time-continuous tunable Gm-C integrator including a "super Gm" differential input stage (O1; MI1/O2, MI2) and using linear and constant degeneration resistors (R1/R2) for obtaining the most optimal linear input-voltage to output-current conversion is tunable in a time-continuous manner. The integrator is provided with three tuning CMOS transistors (MU1, MU2, MU3) controlling the integrating currents flowing between the input stages and from the input stages towards the outputs (OP/ON). By a suitable control of the tuning transistors and owing to the fact that the voltage swing across the latter is small, it is possible to obtain a perfectly linear transconductance (Gm) characteristic over the whole operating range of the integrator.

Abstract: A circuit technique for implementing programmable zeros in high speed CMOS filters is disclosed. The circuit uses both PMOS and NMOS type transconductance elements to implement a biquad with a real zero and two complex poles. The NMOS transconductance element is biased by the total bias current required by several PMOS transconductance elements and can thus provide larger transconductance as required by the equalization function. Programmability is achieved by dividing the NMOS transconductance elements into a plurality of identical sub-elements that are connected in parallel via digitally programmable switches.

Abstract: A cascode circuit includes a source-grounded input NMOS transistor having a gate connected to an input terminal and a drain connected through an output NMOS transistor to an output terminal. An amplification circuit is constructed by a gate-grounded third NMOS transistor having a source connected to the drain of the input transistor, a current mirror circuit consisting of PMOS transistors having an input current path connected to a drain of the third transistor, and a current source connected to an output current path of the constant mirror circuit as a load. An output from the amplification circuit is fed back to a gate of the second transistor. With this arrangement, the cascode circuit can maintain a high output impedance until a minimum output signal voltage reaches around 0.5 V, and can also have a minimum working supply voltage of about 2 V, and at the same time, a circuit construction suitable for IC in the CMOS process.

Abstract: Differential amplifier (10) incorporates five metal oxide field effect transistors (MOSFETs) (M1 to M5). The transistors (M1 to M5) are a source-coupled pair of input transistors (M1, M2) with sources connected to a current control transistor (M5) and having respective drain load transistors (M3, M4). The transistors (M1 to M5) have floating gates (F1 to F5) and input gates (G1 to G5). The amplifier (10) is adjusted to counteract differing input transistor threshold voltage by charging one of the input transistor floating gates (G1 , G2) to reduce amplifier offset voltage extrapolated to zero input transistor drain current. It is then adjusted to reduce discrepancies between actual and design values of input transistor drain voltage by charging one or both of the drain load transistor floating gates (F3, F4). The amplifier may be arranged as an operational amplifier (20) with a second state (16) connected to an input transistor drain.

Abstract: The coupled switching transistors of the digital current switch are connected to a controlled current source. Load resistors of the current switch are formed as controlled resistors. The L-level produced by a reference current branch is compared with a predetermined level by means of a regulating device which includes the reference current branch and a compensator, and the controlled resistor or the controlled current source are adjusted such that the L-level is equal to the predetermined level.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A structure for preventing simultaneous conduction in the power transistors of an output circuit of an audio system includes an auxiliary device in each of the high side control and low side control circuits controlling the power transistors. The auxiliary device in the high side control circuit is turned on simultaneously with the high side power transistor to provide a control signal to the low side control circuit, thereby turning off the low side power transistor. Conversely, the auxiliary device in the low side control circuit is turned on simultaneously with the low side power transistor to provide a control signal to the high side control circuit, thereby turning off the high side power transistor. Thus, simultaneous conduction in the high and low side power transistors is prevented.

Abstract: A differential voltage-current converter has two input transistors and two cross-coupled transistors arranged in a translinear loop, the difference voltage across the emitter resistors of the cross-coupled transistors being equal to the difference voltage across the input terminals. The difference current through the cross-coupled transistors is replicated in the output transistors, thereby enabling a larger output signal amplitude to be obtained. In order to increase the permissible input voltage the bases of the cross-coupled transistors are coupled to the input transistors via emitter-followers. By connecting the collectors of the emitter-followers to the collectors of the output transistors a compensation is obtained for the decreasing current gain at high frequencies.

Abstract: An estimating circuit for application in estimating or deriving the value V.sub.rms.sup.2 or V.sub.peak.sup.2, of a line voltage V.sub.AC provides fast response time and a substantially ripple free value for these signals by the utilization of a controlled harmonic oscillator whose output precisely tracks the input voltage waveform. Two out of phase (by .pi./2) sine wave signals are derived from the input sine wave and these two out of phase signals are squared and summed to derive or estimate the desired square of the sine waveform signal at a fast response time while substantially excluding ripple of the estimated out of phase sine waves. An estimating circuit, described herein, comprises two integrator circuits series connected into a substantially closed loop. The output of the second integrator circuit is fed back to the input of the first integrator circuit. The output of each individual integrator circuit is a voltage sine wave separated in phase from the output of the other integrator by .pi.

Abstract: A master-slave differential comparator having a threshold value. The master section controls the threshold value of the slave section. The slave section is controlled by bias currents therein to matching same in the master section. The bias currents are substantially determined by fixed biases applied to the master section, the difference in biases being substantially equal to the threshold value of the comparator.

Abstract: An operational amplifier circuit includes a differential amplifier having an inverting input, a non-inverting input, and first and second outputs. The differential amplifier is fed by a current source coupled to a power supply voltage. An active load circuit is coupled to the first and second outputs of the differential amplifier and to a ground potential. An additional transistor is provided having a first current-carrying electrode coupled to the first output of the differential amplifier, a second current-carrying electrode coupled to the active load circuit, and an insulated gate electrode coupled to the active load circuit and the second output of the differential amplifier. An inversion amplifier has an input coupled to the second current-carrying electrode of the transistor, and an output, which is fed back through a compensation capacitor to the first output of the differential amplifier.

Abstract: There is disclosed on optoelectronic integrated circuit comprising, a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node, and the common electric power source node being connected through a resistor element to an electric source power supply terminal for supplying an electric source power to the channels.