Abstract: A half-latch that includes negative feedback circuitry is provided. The negative feedback circuitry causes the steady-state gain of the half-latch to remain high so that the overdrive voltage needed to change the state of the half-latch is significantly reduced. Additionally, the negative feedback is bypassed by capacitors at high frequencies so that the speed of the half-latch is substantially unaffected by the negative feedback.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: A dynamic current generator 30 is disclosed in which a common-mode input range is provided which is asymmetric toward the bottom rail VEE. An embodiment of the invention is also disclosed used in an asymmetrical dynamically biased amplifier system 34.

Abstract: There is provided a differential amplifier including: an output terminal through which an output voltage is outputted in response to an input voltage; a first inverter-type input unit connected between a first node and a second node to receive the input voltage; a second inverter-type input unit connected between a third node and a fourth node and receiving a reference voltage and having an output node connected to the output terminal; a circuit biased by an output of the first input unit and configuring a negative feedback loop together with the first input unit; an amplifying unit biased by the output of the first input unit to amplify the output of the first input unit; and a switching unit connected between the first node and the third node and between the second node and the fourth node in response to a voltage level of the output terminal.

Abstract: Methods and systems for increasing gain for an electric circuit may include receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Abstract: An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added capacitance, creates a certain increased voltage drop across the resistor, reducing dv/dt and thus reducing the transient in-rush current into the capacitor. This results in reduced waveform distortion. Such an isolation resistor between a current carrying terminal of a switching bipolar transistor and a current source may be used in various applications, including an emitter follower.

Abstract: Provided is a transconductor circuit for compensating distortion of an output current without reducing the size of chips and operation speed characteristics. The transconductor circuit includes a main circuitry which is a differential pair with source degeneration and to which a predetermined input voltage is applied, an auxiliary circuitry which is connected to nodes of the main circuitry to compensate the distortion of the output current, a variable voltage supply which controls a depth or degree of a distortion compensation operation for the output current, and a current source which supplies the main circuitry with constant bias.

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

Abstract: A driving circuit capable of implementing voltage reduction and attaining high-speed operation and high precision while controlling currents consumed by two through current control transistors independently of each other is obtained. This driving circuit comprises a first differential circuit including a first through current control transistor, a second differential circuit including a second through current control transistor and an output circuit including a first conductivity type first output transistor having a gate supplied with an output of the first differential circuit and a second conductivity type second output transistor having a gate supplied with an output of the second differential circuit. A first potential is supplied to the gate of the first through current control transistor of the first differential circuit while a second potential is supplied to the gate of the second through current control transistor of the second differential circuit.

Abstract: An operational amplifier having a first step-up circuit in the power supply circuit generates a first stepped-up potential level obtained by stepping up a power-supply level with a ground level taken as a reference. A regulator circuit generates a center potential obtained by regulating the first stepped-up potential level by referring to a reference potential level with the ground level taken as a reference. A second step-up circuit generates a second stepped-up potential level obtained by stepping up the center potential with the ground level taken as a reference. A multipotential generating circuit generates a plurality of potential levels from a difference between the second stepped-up potential level and the center potential with the ground level taken as a reference, and supplies those potential levels to the panel of the liquid crystal device that is driven by an MLS driving scheme.

Abstract: A low noise transconductance cell includes a resistor and a differential circuit pair having two equivalent half-circuits. Each half-circuit includes a feedback loop coupled to the resistor. The feedback loop includes an input transistor coupled to an inverting gain stage. The inverting gain stage is coupled to an output transistor which in turn is coupled to the input transistor and the resistor. In a low noise transconductance cell, a bias current source is coupled to the center of series connected resistors. In a high swing transconductance cell, a first bias current source is coupled to the left terminal of a resistance stage and a second bias current source is coupled to the right terminal of the resistance stage. The resistance stage can include a single resistor or a plurality of resistors.

Abstract: An input stage employs low-voltage MOSFETs as input devices for an operational amplifier circuit that operates at common mode voltages that may exceed the gate-oxide breakdown voltage of the input devices. Also, the input stage is arranged for relatively low noise. The input stage is arranged to detect the input common mode voltage and to feed back the detected input common mode voltage to a base of a bipolar folded cascode transistor that is coupled to the drain of the input devices. Accordingly, the input devices are bootstrapped such that they are protected from gate-oxide breakdown.

Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: A biasing technique between a first circuit stage and a second circuit stage is described. Specifically, the technique comprises using a combination of thin and thick oxide transistors.

Abstract: A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair.

Abstract: An integrated circuit comparator includes a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: An output circuit device has an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor. A control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.

Abstract: A current source circuit with differential gain boosting is provided. The current source circuit differentially provides first and second currents. The first current is produced by a first cascoded current source, and the second current is produced by a second cascoded current source. Each of the cascoded current sources comprises a current source transistor and a cascode transistor. The current source circuit has high output impedance because a voltage associated with a gate of the cascode transistor of the first cascoded current source and another voltage associated with a gate of a cascode transistor of the second cascoded current source are each forced to an approximately constant voltage by a differential amplifier. The drain voltage of the first and second current source transistors are each servoed to the saturation drain to source voltage of the first current source transistor.

Abstract: In a master block, the exponential conversion characteristic is determined on the basis of a common mode reference voltage and a reference voltage. In a slave block, the exponential conversion characteristic determined with the master block is used to create a control voltage and a gain control signal on the basis of a common mode reference voltage and a reference voltage. For example, a gain of the variable gain amplifier is controlled by using this gain control signal.

Abstract: A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

Abstract: A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage.

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.

Abstract: The present invention provides systems and methods related to a variable gain amplifier. The variable gain amplifier includes a first differential amplifier, a second differential amplifier, a combining circuit, and a current control circuit. The first differential amplifier circuit and the second differential amplifier circuit share a common input signal and have different amplification degrees. Each of the first and second differential amplifier circuits includes a first transistor and a second transistor that form a differential pair. The first transistor and the second transistor of each differential amplifier circuit have bases that are supplied with the input signal, and collectors that output signals to the combining circuit. The current control circuit changes a ratio between a bias current of the first differential amplifier circuit and a bias current of said second differential amplifier circuit based on a gain control signal.

Abstract: The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the input stage, a CMFB circuit and an output stage, at which an amplified differential output voltage is output. In order to improve the stability of a common-mode regulating loop, a current source is provided, which additionally feeds current into the regulating loop and thereby ensures that a control voltage for the load does not fall below a predetermined value.

Abstract: A differential charge pump includes common mode circuitry for supplying a common mode voltage to a charging capacitor in the charge pump. The gate voltage of a reference transistor in a biasing branch of the differential charge pump is adjusted until the drain voltage of the reference transistor is equal to the common mode voltage when a specified bias current is flowing through the biasing branch. The same gate voltage and bias current are provided to a first transistor in a first common mode branch and a second transistor in a second common mode branch. The drains of the first transistor and the second transistor are connected to a first plate and a second plate, respectively, of the charging capacitor. In this manner, a desired common mode voltage is supplied to the charging capacitor.

Abstract: A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.

Abstract: A fully integrated charge amplifier with DC stabilization includes a first amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal of the first amplifier, a transimpedance amplifier having an input terminal coupled to the output terminal of the first amplifier and an output terminal, and an impedance device coupled between the input terminal of the first amplifier and the output terminal of the second amplifier. The impedance device has a resistance of at least 1 M?.

Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: A method for detecting a null current condition in a PWM driven inductor connected between a voltage source node and a second circuit node of a line for outputting current to a load includes generating a derivative signal by time differentiating a voltage on the second node. The method further includes monitoring an instant when the derivative signal becomes negative, and signaling verification of the null current condition each time the derivative signal becomes negative.

Abstract: Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.

Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.

Abstract: A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: A differential voltage amplifier includes a dynamic level shifter circuit and an amplifier circuit. The dynamic level shifter circuit includes high-impedance current sources and resistors that are arranged to move the common-mode levels of a differential input signal to a signal level that is suitable for the amplifier circuit. The amplifier circuit may be single-ended or differential. The dynamic level shifter circuit may include one or more current sources that are arranged to provide improved performance for low common-mode levels. A dynamic biasing scheme may be employed to improve operation over varied common-mode ranges. A trimming circuit may be used to adjust offsets in the system. A DC chop arrangement may be employed to remove offsets in the system.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: An exponentially variable gain mixer circuit includes an oscillating circuit generating an alternating differential signal. A correction circuit is connected to the oscillating circuit and includes a first amplifier and a differential amplifier. The first amplifier receives an external gain variation command and generates a differential output signal that includes a control voltage and a bias voltage. The differential amplifier receives the alternating differential signal and generates a differential modulation signal. A variable gain mixer receives an input differential signal and generates an amplified differential signal as a function of the differential modulation signal and the control voltage.

Abstract: Digitally-controlled, variable-gain mixers and amplifiers are provided which couple transconductance cells to receive respective tap signals from a fixed attenuator that receives a first input signal. A gain interpolator provides first and second control currents with amplitudes that correspond to a segment of a control word and a multiplexer responds to another control-word segment by routing the control currents to a selected pair of adjacent transconductance cells. In response, the transconductance cells provide amplifier current signals which can also be routed to a transistor switch that mixes them with a second input signal to generate a mixer output signal whose amplitude corresponds to the control word.

Abstract: A first differential amplifier circuit includes a first P-type transistor and a second P-type transistor which constitute a current mirror circuit, and operates based on an input voltage VIN. A second differential amplifier circuit includes a first N-type transistor and a second N-type transistor forming a current mirror circuit and operates based on the common input voltage VIN. A third P-type transistor operable based on a first signal S1 from the first differential amplifier and a third N-type transistor operable based on a second signal S2 from the second differential amplifier are provided. A voltage between these third P-type and third N-type transistors becomes an output voltage VOUT.

Abstract: A dynamic current generator 30 is disclosed in which a common-mode input range is provided which is asymmetric toward the bottom rail VEE. An embodiment of the invention is also disclosed used in an asymmetrical dynamically biased amplifier system 34.

Abstract: Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Abstract: A comparator circuit includes a differential amplifier including load resistors, for amplifying difference between two input voltages of the comparator circuit; an emitter follower circuit for applying positive feedback with respect to a differential amplifier and outputting an output voltage of the comparator circuit; and a grounded-base amplifier, and outputting an output voltage of the comparator circuit, for realizing both voltage output and current output. A grounded-base amplifier includes two transistors each of which has a base supplied with a reference voltage. The differential amplifier includes two load resistors respectively connected to each emitter of the transistors of the grounded-base amplifier. The load resistor flowing a current which is obtained through a collector of the transistor as an output current of the comparator. With this arrangement, it is not necessary to provide a current switch circuit for obtaining current output of the comparator circuit.

Abstract: A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: The invention relates to a conversion circuit to convert a differential power signal II[1], II[2] into a differential output current IC[1], IC[2], said circuit including conversion means CONV and regulation means REG for the input impedance of the circuit connected to the conversion means CONV. The regulation means REG according to the invention include negative feedback means to control a regulating current IREG taken from each component of the power signal II[1], II[2] as a function of the values of the potentials V[1], V[2] at the inputs of the conversion circuit. The half-sum between the two potentials V[1], V[2] at the inputs of the circuit is advantageously used to guide the negative feedback which can advantageously be applied to the bases of the regulation transistors controlling the value of the regulating current.

Abstract: In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching.