Abstract: The present disclosure provide an electronic device. The electronic device includes a voltage generator and a low drop-out (LDO) circuit. The voltage generator has an input and an output. The LDO circuit has an input electrically connected to the output of the voltage generator. The voltage generator includes a first voltage regulator having a first terminal and a second terminal. The first terminal of the first voltage regulator is electrically connected to the output of the voltage generator.

Abstract: A semiconductor device includes a plurality of functional blocks, each being configured to provide at least one predetermined function. The functional blocks at least include a first functional block and a second functional block. The first functional block and the second functional block are coupled in serial with a predetermined current flowing therethrough.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: An apparatus includes a surface acoustic wave (SAW) sensor. The SAW sensor includes a piezoelectric substrate. The SAW sensor also includes first and second interdigitating transistors over the piezoelectric substrate. The first interdigitating transistor is configured to convert an input electrical signal into an acoustic wave. The second interdigitating transistor is configured to convert the acoustic wave into an output electrical signal. The piezoelectric substrate is configured to transport the acoustic wave. The SAW sensor further includes a detection layer over the piezoelectric substrate and positioned at least partially between the first and second interdigitating transistors. The detection layer includes (i) antibodies configured to bind to one or more biological analytes and (ii) a hydrogel layer over the antibodies.

Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device that reduces or eliminates a voltage imbalance by implementing at least one stage in a stacked switch device with a different width, and thus the voltage applied to each stage in the OFF state may be more equally distributed among the individual stages.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.

Abstract: A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: A differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Abstract: According to an aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, where at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

Abstract: Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.

Abstract: This application relates to a full duplex communication device. In one aspect, the device includes a transmission/reception antenna configured to receive a received signal corresponding to a transmitted signal. The device may also include an analog cancellation unit configured to set values of elements constituting an analog cancellation circuit and cancel an interference signal included in the received signal using the set values of the elements constituting the analog cancellation circuit. The device may further include a digital cancellation unit configured to cancel a remaining interference signal included in the received signal. Some embodiments can minimize the influence of distortion of a transmitted signal due to non-linearity of a power amplifier during an active analog self-interference cancellation process.

Abstract: The disclosure provides a charging device, which includes an input terminal configured to receive an input voltage; an output terminal configured to connect a target load so as to charge the target load; a control terminal, configured to receive a control voltage; a junction field-effect transistor and a control circuit. The junction field-effect transistor includes at least: a drain, electrically connected to the input terminal so as to receive the input voltage; a source, electrically connected to the output terminal so as to output an output voltage and an output current; and a gate, electrically connected to the control terminal. The control circuit is electrically connected to the control terminal, and configured to change the control voltage based on a change in a load voltage so as to change a pinch-off voltage of the JFET by controlling a bias voltage on the gate, thereby controlling the output current.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level which is lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract: A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract: A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.

Abstract: An integrated circuit is provided. A standard cell includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS transistors are disposed in a first row and a second row in the semiconductor substrate. The NMOS transistors are disposed in a third row in the semiconductor substrate. The third row is adjacent to the first and second rows and arranged between the first and second rows.

Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Abstract: An integrated circuit includes a power transistor and a drive circuit. The drive circuit includes at least one drive transistor. The power transistor and the at least one drive transistor are integrated in a common semiconductor body. The power transistor includes at least one transistor cell with a source region, a body region, a drift region, a drain region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The at least one drive transistor includes active device regions integrated in a well-like structure comprising dielectric sidewall layers.

Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

Abstract: There are disclosed herein various implementations of a half-bridge or multiple half-bridge switch configurations used in a voltage converter circuit using at least two normally ON switches. Such a circuit includes a high side switch and a low side switch coupled between a high voltage rail and a low voltage rail of the voltage converter circuit. The high side switch is coupled to the low side switch at a switch node of the voltage converter circuit. At least one group IV enhancement mode switch is used as an enable switch. The group IV enhancement mode enable switch may be an insulated gate bipolar transistor (IGBT), a super junction field-effect transistor (SJFET), a unipolar group IV field-effect transistor (FET), or a bipolar junction transistor (BJT).

Abstract: An integrated circuit for controlling a boost converter. The integrated circuit includes a gate pin, a source pin, a feedback pin, a current mirror sub-circuit, and a control sub-circuit. The current mirror sub-circuit is connected to the source pin to produce an output current from a reference current flowing between the source pin and ground, the reference current being larger than the output current.

Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.

Abstract: A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.

Abstract: A semiconductor circuit provides at least one first electrical pin with multiple signal assignment or potential assignment in order to integrate several circuit variants in the semiconductor circuit. It has a switch element for isolating or connecting at least one first electrical pin from or to an input or output of a functional unit integrated in the semiconductor circuit.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract: A System on a Chip (SoC) has a first set of switches, each having first terminals for routing SoC signals and a second terminal, and a second set of switches. Each switch of the second set of switches has third terminals for routing signals with the first set of switches, and a fourth terminal. A SoC control module defines a switching configuration, and includes a first memory portion for storing a first switching protocol for the first set of switches. This defines, for a switch of the first set of switches, an electrical path between one of the first terminals and the second terminal. A second memory portion stores a second switching protocol for the second set of switches, and defines, for a switch of the second set of switches, an electrical path between one of the third terminals and the fourth terminal.

Abstract: Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor.

Abstract: Disclosed herein are solid state fault isolation devices and methods. According to one or more embodiments, a semiconductor current fault controlled device is provided. The device includes a semiconductor substrate of N-type conductivity. The substrate has opposed major surfaces. An anode region of P-type conductivity is formed in one major surface. A P-type buried layer is formed in a first portion of the other major surface. A junction field-effect transistor (JFET) is formed in a second portion of the other major surface. A P-type top layer is formed in the JFET and forms a channel defined by an overlap between the P-type buried layer and the P-type top layer. The channel laterally extends to the semiconductor substrate from a cathode region and being shielded from the anode region.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.

Abstract: A highly reliable semiconductor device in which a shift in threshold voltage of a transistor due to deterioration can be inhibited is provided. A pulse output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. A clock signal is supplied to a drain of the first transistor. A first power supply potential is applied to a source of the second transistor, and a drain of the second transistor is connected to the drain of the first transistor. A second power supply potential is applied to a drain of the third transistor. The first power supply potential is applied to a source of the fourth transistor, and a drain of the fourth transistor is connected to the drain of the third transistor. The first power supply potential is applied to a source of the fifth transistor, and a drain of the fifth transistor is connected to a gate of the third transistor.

Abstract: A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.

Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.