Unijunction Transistor Patents (Class 327/569)
  • Patent number: 10062928
    Abstract: A method for charging batteries that have at least one metal electrode or at least one metal-based compound electrode includes applying a DC signal to the batteries and applying an AC signal to the batteries. The DC signal and AC signal may be combined as a composite signal, which is applied to the batteries, or may be applied to the batteries as separate, independent signals, during a charging cycle. As such, the DC signal serves to charge the batteries, while the AC signal operates to suppress, avoids or reverse the growth of dendrites in the batteries. As a result, the operating life of the batteries is extended, and the electrical storage capacity of the batteries is preserved.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: August 28, 2018
    Assignee: The University of Akron
    Inventors: Homero Castaneda, Roberto Hernandez Maya
  • Patent number: 9664729
    Abstract: Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 30, 2017
    Assignee: NXP USA, Inc.
    Inventors: Randall C. Gray, Ibrahim S. Kandah, Philipe J. Perruchoud, John M. Pigott, Thierry Sicard
  • Patent number: 6911862
    Abstract: A band gap voltage reference for an NMOS memory device includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region, and a collector formed by the NMOS memory device n+ drain region, in which the base/channel region is less than 0.4 ?m in width and advantageously may be fabricated by standard flash memory manufacturing processes.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: June 28, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Alessandro Torsi
  • Patent number: 5430407
    Abstract: A series of squarer circuits each providing an ideal square law transfer character comprises at least one backward diode and a compensating resistor connected in series therewith. A second backward, diode can be included connected front to back with the one diode.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: July 4, 1995
    Inventor: Xianzhi Dong