Abstract: A sense amplifier includes a differential circuit comparing data in memory cells and reference data in reference cells. The sense amplifier is provided with a first reference cell corresponding to a predetermined value of the threshold of a memory cell, a second reference cell corresponding to the determination of the memory cell having a high level at the time of high temperature or low temperature and a third reference cell corresponding to the determination of the memory cell having a low level at the time of high temperature or low temperature. The sense amplifier can thereby detect at room temperature a memory cell which would be defective at high temperature or low temperature.

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract: A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier.

Abstract: The inverter functioning as a comparator, dummy inverter having the same electric characteristics as the inverter, and control circuit are provided. Vth detecting input voltage output from the control circuit is input into the dummy inverter, Vth detecting output voltage output from the dummy inverter is input into the control circuit, and the threshold voltage of the dummy inverter is detected. The threshold voltage of the inverter is controlled by controlling the back gate voltages of the MOS transistors of the dummy inverter and the inverter in such a manner that the threshold voltage of the dummy inverter coincide with an external reference voltage.

Abstract: A comparator circuit for comparing a differential input signal to a reference signal. A differential MOS transistor pair is provided having respective gates for receiving the positive and negative components of the differential input signal. A tail current source is coupled to the common sources of the transistor pair, with the current magnitude being related to the reference signal magnitude. The first and second transistors are made differently, typically by making the sizes different, so that the gate-source voltages differ when the transistor currents are equal. A comparator stage provides a digital output which changes state when the transistor currents are equal, with the difference in gate-source voltage representing the comparator trip voltage, a trip voltage related to the magnitude of the reference signal.

Abstract: The sense amplifier compares an input signal characterizing the content of the memory device which is to be read with a threshold value which can be changed or selected on the basis of the output signal from the sense amplifier. The use of such a sense amplifier makes it possible to reduce the risk of the content of a memory device which is to be read being determined incorrectly to a minimum.

Abstract: A low voltage reset circuit device without being influenced by temperature and manufacturing process is formed by a first low voltage reset circuit using an energy gap circuit to generate a reference voltage, and a second low voltage reset circuit using a threshold voltage of a MOS transistor as a reference voltage. The first low voltage reset circuit is used to provide an accurate low voltage reset property,. while the circuit only works as VDD>1.2V. When VDD<1.2V, the second low voltage reset circuit still works normally for providing the desired reset signal thereby covering the low VDD voltage range.

Abstract: The present invention provides a single-ended signal detection circuit (sense-amplifier) which exhibits a little power consumption and performs a high speed operation. A sense-amplifying circuit (100) detects a signal on one signal line to amplify the detected signal. A sensing switch composed of first and second switches (13, 14), each of which is connected to a source terminal of the sense-amplifying circuit and to a constant current source (15), the first switch being connected to a signal line (10) and the second switch being connected to a reference potential (Vref), wherein a driving force of the first switch is larger than that of the second switch.

Abstract: A Flash memory sense amplifier precharge device having a self-bias circuit and a precharge circuit. The self-bias circuit is coupled to precharge a data node in response to a first control signal. The precharge circuit is coupled to precharge the data node in response to a second control signal, wherein the precharge circuit aids the self-bias circuit precharge the data node faster than the self-bias circuit could itself.

Abstract: A two-stage filter for a circuit protection device. The filter includes a first filtering device connected to receive an input signal v, the first filtering device generating an intermediate signal v1, wherein v 1 ⁢ ( k ) = ∑ n = 0 20 ⁢ h n · v ( k - n ) , where k is a sample index and h0 . . . h20 are first filter coefficients.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently vary small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: A high speed sense amp supplies current to a bit line connected to a memory cell transistor and also detects a potential of the bit line. The potential of the bit line varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a first potential and the bit line. A second transistor is connected between the first potential and the bit line. The bit line is input to an inverter that has its output terminal connected to a gate of the first transistor. A differential amp has a first input terminal connected to a reference potential and a second input terminal connected to a node between the load element and the first transistor. The output of the differential amp indicates a difference between the reference potential and the bit line potential.

Abstract: A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.

Abstract: An output circuit is driven by a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.

Abstract: A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node.

Abstract: A high speed sense amp supplies current to a bit line connected to a memory cell transistor and also detects a potential of the bit line. The potential of the bit line varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a first potential and the bit line. A second transistor is connected between the first potential and the bit line. The bit line is input to an inverter that has its output terminal connected to a gate of the first transistor. A differential amp has a first input terminal connected to a reference potential and a second input terminal connected to a node between the load element and the first transistor. The output of the differential amp indicates a difference between the reference potential and the bit line potential.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages. Additionally, there is provided a method for sensing logic levels in a memory device. According to the method, a bit line is polarized at a polarization voltage level, and a first signal representative of a current flowing through a memory cell is compared with a second signal representative of a reference current. The polarization voltage level is independent of the supply voltage level.

Abstract: Providing an active signal that increases the gate overdrive voltage of the driver of a sense amplifier enables the use of smaller drivers. This facilitates more efficient layouts and/or smaller sense amplifiers, thereby reducing the chip size.

Abstract: A current sense amplifier circuit using a dummy bit line is provided. The current sense amplifier circuit includes a cell current generator, a reference current generator, and a sense amplifier. The cell current generator includes a memory cell connected to a word line and a bit line and generates memory cell current applied to the memory cell and bit line charge current for charging the bit line. The reference current generator includes a dummy bit line and a reference cell and generates reference cell current applied to the reference cell and dummy bit line charge current for charging the dummy bit line. The sense amplifier includes a first input terminal, connected to the cell current generator, for receiving the memory cell current and the bit line charge current and a second input terminal, connected to the reference current generator, for receiving the reference cell current and the dummy bit line charge current.

Abstract: A voltage follower and a semiconductor integrated circuit including the voltage follower. In the voltage follower, an output voltage Vout from a source follower output transistor 8 is negative fed back to a gate electrode of the source follower output transistor 8 via a differential amplifier 1. A clamp circuit 28 is provided which clamps the gate potential of the source follower transistor 8 by using a source and backgate potential of the source follower transistor 8, that is, potential at an output terminal 53, as a reference potential. Since the source-gate voltage of the source follower transistor 8 is clamped at a predetermined voltage and thus the maximum electric field applied to the gate oxide film is reduced, it becomes possible to use a MOS transistor having thin gate oxide film and short channel length and having high current drive ability, as a source follower transistor, even when a power supply voltage is high.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently very small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 m Volt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A semiconductor integrated circuit device for a magnetic disk apparatus has analog circuits such as a read/write circuit and digital circuits such as an interface driver circuit, a control circuit, and a stepping motor driver circuit, all of these circuits operating on a single supply voltage. The semiconductor integrated circuit device further has a voltage regulator whose output voltage is lower than the supply voltage and variable according to the voltage applied to an output voltage adjustment terminal. The control circuit operates on the output voltage of this regulator.

Abstract: A sense-amplifier circuit for a multivalued information storing memory is featured by a reduced current consumption realized without any elongation of delay time, which circuit comprises plural current-mirror sub-sense-amplifiers corresponding to plural reference potentials VREF, wherein those having higher reference potentials among the sub-sense-amplifiers are provided each with a current-limiting switching element QNX.

Abstract: A class AB amplifier (400) is disclosed, having a first input node (402), a second input node (404), and an output node (406). A push-pull input stage (412) includes cross-coupled pairs of transistors, which form a charge current path and a discharge current path. When the voltage at the first input node (402) is greater than the voltage at the second input node (406), the amount of current drawn in the charge current path increases, and the amount of current drawn in the discharge current path decreases. When the voltage at the first input node (402) is less than the voltage at the second input node (404), the amount of current in the charge current path decreases while the amount of current in the discharge path increases. A first and fourth current mirror (422 and 428) are coupled to the charge current path, and a second and third current mirror (424 and 426) are coupled to the discharge current path.

Abstract: A sense amplifier may include a pair of output terminals, an evaluation circuit, a reference circuit and a pair of clamping circuits. The evaluation circuit connects a first output terminal to an evaluation potential. It receives a data signal at an input terminal. The reference circuit connects a second output terminal to the evaluation potential. The reference circuit receives a pair of reference signals on other input terminals. The clamping circuits each couple a respective one of the output terminals to a precharge potential. Inputs of each clamping circuit are coupled to the other of the output terminals.

Abstract: An electronic load circuit provides a variable load current at a high amp level, at low-voltage so that contemporary voltage supplies of perhaps 1.5V may be tested. This load is used for testing voltage supply circuits for computer systems or the like. A number of parallel, high-current MOS transistors of low internal resistance are used as a constant-current load. Current in the load path is sensed by a sensing resistor connected in series with all of the transistors, and this resistor has a value of the order of the effective internal resistance of the source-to-drain paths of the parallel transistors and connecting links to these transistors via a circuit board, connector terminals, etc. The sensing resistor provides a feedback signal to a high-gain op-amp, the output of which is compared to a variable input signal to produce a gate drive voltage for the transistors. The input signal may be varied to simulate the variable loading exhibited by a computer system.

Abstract: The present invention is directed to an integrated circuit comprising a voltage source and a voltage sensing circuit having a switch circuit for sensing a switch voltage and a switch current; a voltage comparison circuit connected to the switch circuit for comparing the switch voltage to a limiting voltage; and a current limiting circuit connected to the switch circuit and the voltage comparison circuit, which is capable of limiting the switch current when the switch voltage reaches or exceeds the limiting voltage. In a preferred embodiment of the invention the switch circuit is a bi-directional switch circuit and the voltage comparison circuit incorporates a series of Zener diodes, wherein the current limiting circuit is a current foldback circuit.

Abstract: A sense-amplifier circuit comprising a plurality of sub-sense-amplifiers corresponding to respective reference potentials can operate fast when used for a multivalued information memory. The sense amplifier circuit is composed of sub-sense-amplifiers having different polarities according to corresponding reference potentials: a sub-sense-amplifier SN3 having the highest reference potential is of N (polarity) type and a sub-sense-amplifier SP1 having the lowest reference potential is of P (polarity) type. All sub-sense-amplifiers can operate according to improved characteristics assuring a reduced access time.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: The average value of an input signal supplied to an input terminal is generated by an integrating circuit consisting of a series circuit of a capacitor, a constant-current source transistor, and a resistor. The average value is used as the reference voltage for the differential amplifier circuit. Further, to each of differential pair transistors the sources of which are commonly connected, other transistors are cascode connected, respectively. Supplied to each gate of the cascode connected transistors is a divisional voltage of the differential voltage between the average voltage from the integrating circuit and the circuit power supply voltage, which divisional voltage is obtained by a capacitive divider circuit.

Abstract: An input receiver circuit which is capable of reducing a difference between a propagation time at the rise-up and that at the fall of an input signal and is suitably used for semiconductor memory devices. The input receiving circuit comprises a node, six N channel (N-ch) MOS transistors and two P channel (P-ch) MOS transistors. The first and second N-ch transistors receive an activation signal and have grounded sources. The third and fourth N-ch transistors receive the first and second signal and have sources connected to the drains of the first and second N-ch transistors, respectively. The fifth and sixth N-ch transistors have gates connected to the node and are provided in parallel to the third and fourth N-ch transistors, respectively. Sources of the first and second P-ch transistors are supplied with the power source voltage. Drains of the first and second P-ch transistors are connected to the drains of the third and fourth N-ch transistors, respectively.

Abstract: A p-well region (16) is formed in the main surface area of an n-type semiconductor substrate (11). A potential (V.sub.BB) which is lower than an externally input potential is applied to the p-well region (16). In the surface area of the p-well region (16), a first impurity diffused layer (12) of n-type to which the externally input potential (Vin) is applied and a second impurity diffused layer (13) of n-type to which a reference potential is applied are formed. The first impurity diffused layer (12) serves as the drain region of a first MOS transistor (Q9) of n-channel formed in the p-well region (16) and the second impurity diffused layer (13) serves as the drain region of a second MOS transistor (Q10) of n-channel which is also formed in the p-well region (16). The first and second MOS transistors (Q9 and Q10) constitute the input section of an input circuit.

Abstract: A frequency stabilizer circuit in the form of a charge-pump phase-lock loop utilizing a MEMS capacitance device, preferably a tunable MEMS capacitor or a MEMS capacitor bank, which more rapid and with a greater precision determine the phase and frequency of a carrier signal so that it can be extracted, providing an information signal of interest. Such MEMS devices have the added advantage of providing linear capacitance, low insertion losses, higher isolation and high reliability, they run on low power and permit the entire circuit to be fabricated on a common substrate. The use of the MEMS capacitance device reduces unwanted harmonics generated by the circuit's charge pump allowing the filtering requirements to be relaxed or perhaps eliminated.

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.

Abstract: A leakage tolerant sense circuit for use in an electrically programmable and erasable read only memory (EEPROM) is disclosed. In a reference portion of a sense cycle, the leakage tolerant sense amplifier utilizes the sum of a reference current and any leakage current to establish a reference voltage. In the subsequent sense portion of the sense cycle, the leakage tolerant sense amplifier utilizes the sum of a memory cell current and any leakage current to establish a read voltage. The read voltage is compared with the reference voltage to determine the logic stored within the memory cell.

Abstract: A differential amplifier circuit has a differential amplifier circuit section for amplifying a difference voltage between an inverting input node and a non-inverting input node, and an output buffer circuit for outputting, to an output node, the amplified difference. The differential amplifier circuit section is connected to a first high potential power supply node and a first low potential power supply node, and is driven by potentials applied to the first high potential and first low potential power supply nodes. The output buffer circuit is connected to a second high potential power supply node and a second low potential power supply node, and is driven by potentials applied to the second high potential and low potential power supply nodes.

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs.

Abstract: An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both.

Abstract: The circuit for sensing a memory having a plurality of threshold voltages is directed to using a technique for maintaining a characteristic curve of a voltages-matched circuit and combining a characteristic curve in which the voltage is moved by a minimum value which is one half of the reference voltage with a conventional characteristic curve, so that it is possible to reduce in half the minimum distance between the voltage distributions for thereby optimizing the above distance by controlling the power voltage irrespective of the characteristic of a device.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.

Abstract: A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

Abstract: A sense amplifier increases the differential voltage between a reference signal and a sense signal by using a current mirror to control the generation of the reference signal and the sense signal responsive to a common control signal. The sense amplifier includes a reference signal generator for generating the reference signal at a reference node responsive to a reference cell, a sense signal generator for generating the sense signal at a sense node responsive to the state of a memory cell, and a differential amplifier for amplifying the voltage difference between the reference signal and the sense signal. The reference node is coupled to the reference cell which discharges current from the reference node, and the sense node is coupled to the memory cell which discharges current from the sense node. The reference signal generator includes a first current source transistor that is coupled between a power supply terminal and the reference node.

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

Abstract: A method and device for maintaining junction isolation between a second region that is normally clamped at a reference potential, contained within a first region of an opposite type of conductivity whose potential is subject to large inertial swings. The junction is ensured even when the potential of the first region moves toward and beyond the reference potential to which the second region is clamped, by connecting the second region to the reference potential by a switch, and causing the switch to open which places the second region in a floating state, leaving it free to track the potential excursion of the first region. The switch is closed after the potential of the first region has returned to a normal value. A comparator senses a shift of the potential of the second region from the reference potential to which it is clamped. The shift is dynamically induced by the capacitive coupling of the two regions, and triggers off the clamping switch.

Abstract: To read out a data bit stored in a memory cell including a programmable resistor memory element, a first voltage is developed on a first sense node due to initiation of current flow through the memory element and a second voltage is developed on a second sense node due to current flow through a reference resistor. The first and second voltages are separately detected to generate a trip signal in response to a leading edge of either of the first and second voltages achieving a threshold level. A flip-flop circuit is conditioned by the trip signal to produce opposite logic signal voltages on the first and second sense nodes indicative of the binary value of the stored data bit.

Abstract: A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.