Abstract: A system including a power modulation device and an active voltage balancing system is provided. The power modulation device includes first and second semiconductor switches in series. The active voltage balancing system includes a differential voltage logic configured to detect a voltage difference between the first and second semiconductor switches and edge capture logic configured to detect a time difference between when the first and second semiconductor switches are switched. The active voltage balancing system further includes a micro-controller configured to output first and second gate drive signals to drive the first and second semiconductor switches. The micro-controller is configured to tune the first and second gate drive signals based on the voltage difference to compensate for voltage imbalance and the time difference to compensate for drive signal asymmetry to actively balance a voltage between the first and second semiconductor switches.

Abstract: In one embodiment, an apparatus includes a first transistor where the base of the first transistor is coupled to an input node. A second transistor is provided where the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to an output node. A third transistor is provided where the base of the third transistor is coupled to the input node. A fourth transistor is provided where the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output node and the base of the second transistor is coupled to the base of the fourth transistor. The base of the second transistor is coupled to the base of the fourth transistor through a shorting link.

Abstract: A temperature-independent current source is provided, which includes a current source generating a current that is proportional to the temperature and a current source generating a current that is inversely proportional to the temperature. Values of the circuit elements are selected so that the currents of the current sources add up to a substantially temperature-independent current. Related current sources utilize dual-base Darlington bipolar transistors to generate a temperature-independent current.

Abstract: There is provided a current switching circuit that adds additional current in accordance with an intensity of output current to input current of a current mirror at a rising edge of the output current of the current mirror. The current switching circuit includes a MOS transistor outputting the additional current upon receiving ON potential at a gate terminal, and a slope of a leading edge waveform of a pulse signal providing the ON potential is controlled in accordance with the intensity of the output current.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: A drive with a high impedance input, low impedance output is created. When a switching or driving action requiring the sourcing and sinking of current from a common node in a wide frequency range is desired, the invention allows the creation of a simple, efficient, two switch drive system that functions across a wide range of conditions. The circuit uses a discrete N-Channel FET paired with discrete PNP transistors. A high impedance input node is formed by connecting the FET gate to the transistor base. The differential threshold voltage that exists between the FET gate and the transistor base prevents the two devices from generating conflicting currents at the output node formed by the common source emitter. The circuit further lends itself to output waveform variations as may be required for various drive strategies by manipulating the input signal processing to custom modify the resulting output voltage and current.

Abstract: A semiconductor device is provided which includes a first unipolar transistor provided in a front stage of the device, second unipolar transistor provided in the front stage, and a bipolar transistor provided in a rear stage of the device. In this semiconductor device, drain and the source of the first unipolar transistor are connected to collector and the base of the bipolar transistor, respectively, and drain and the source of the second unipolar transistor are connected to emitter and base of the bipolar transistor, respectively.

Abstract: A direct current controlled differential base voltage generating circuit, applicable to a gain control of an RGB video amplifier for controlling a contrast by a voltage generating circuit in which an input control signal has a voltage within a set range, has a high input impedance. Since a differential base voltage is controlled by an input control signal applied thereto through bases of PNP Darlington-connected transistors, the circuits high input impedance can provide operation when a voltage of the input control signal is about 0 volts. Therefore, the direct current controlled differential base voltage generating circuit can easily interface with a computer controlled alignment system.

Abstract: In order to stabilize the idle current and the bandwidth of a Darlington-coupled output stage, the output stage is adapted, within an interval of currents, to continuously increase its current amplification with increasing input current from a first amplification value to a second amplification value.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An output circuit, for minimizing output idle current fluctuations and improve the output voltage range, has first and second transistors connected to first and second power sources, with a plurality of diodes connected to control terminals of the first and second transistors. The output circuit further includes a third transistor having a first terminal connected to the second power source and a second terminal connected to a predetermined position among the plurality of diodes. A predetermined voltage is applied from the diodes to the control terminal of the first transistor when the third transistor is saturated, to bring a level of an output of said output circuit close to a level of the second power source. A fourth transistor, a fifth transistor, a first resistor, and a capacitor are also provided.

Abstract: An output circuit has a bipolar transistor circuit of a 1st and a 2nd bipolar transistor connected in Darlington configuration. The base of the 1st transistor is supplied with an input signal. The collector of the 2nd transistor is connected to a power supply through a 1st diode. And, a signal is outputted from the emitter of the 2nd transistor. The output circuit also includes a 1st PMOS transistor. The source of the 1st PMOS transistor is connected to the base of the 2nd transistor, its drain being grounded, and its the backgate being connected to the power supply through the 1st diode. The output circuit may further includes a 2nd PMOS transistor having a source and a backgate both connected to the power supply, a drain connected to the base of the 2nd transistor through a second diode, and a gate supplied with an inverting signal of the input signal.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A direct-current stabilizer includes an n-p-n transistor as a control transistor, and a control terminal to which a control voltage for driving the control transistor is applied. The value of the control voltage is determined so that a voltage applied to the base of the control transistor is not lower than the sum of the emitter voltage and the base-emitter voltage. With this structure, since the control transistor is driven by the control voltage of a value different from that of the input voltage, it is possible to limit the input voltage to a low value, allowing the difference between the input voltage and the output voltage to be minimized. Moreover, it is possible to switch the output of the direct-current stabilizer by connecting to the control terminal a transistor for switching the application of the control voltage to the control terminal between on and off. Furthermore, when the control terminal is connected to the input terminal, the control transistor is driven by the input voltage.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A driver circuit comprises a current mirror circuit including an output transistor, a load connected to a main electrode of the output transistor, and current supplying device for supplying a current to a control electrode of the output transistor. The output transistor controls a current flowing through the load.

Abstract: A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.

Abstract: An amplifier circuit (10) is provided. Amplifier (10) has an amplifier stage (14) that is coupled to control an output stage (18). Output stage (18) includes a sourcing circuit (20) and a sinking circuit (22). Output stage (18) also includes a mirror circuit (42) that is coupled to an output of amplifier stage (14). Output stage (18) also includes a current balancing circuit (30) coupled to mirroring circuit (42) and sourcing circuit (20). Mirroring circuit (42) draws current from balancing circuit (30) in response to a first predetermined output from amplifier stage (14) such that balancing circuit (30) causes an insignificant current to flow in sourcing circuit (20). Thus amplifier (10) operates to sink current from an external load (12). Alternatively, mirroring circuit (42) may draw an insignificant current from balancing circuit (30) in response to a second predetermined output of the amplifier stage (14). This causes a significant current flow in sourcing circuit (20).

Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on.

Abstract: A multiplier circuit includes first and second squaring circuits each having a differential input terminal pair. A first input terminal of the differential input terminal pair of the first squaring circuit is applied with a first input voltage and the second input terminal thereof is applied with a second input voltage opposite in phase to the first input voltage. A first input terminal of the differential input terminal pair of the second squaring circuit is supplied with the second input voltage and the second input terminal thereof is applied with the first input voltage. The first and second squaring circuits each includes two sets of unbalanced differential transistor pairs which are arranged so that their inputs are opposite in phase and their outputs are connected in common. The transistors of each unbalanced differential transistor pair have different emitter sizes.

Abstract: A power output stage has a Darlington-pair circuit (11, 12) for switching an inductive load, especially the ignition coil of an internalcombustion engine. In order to predetermine the operating mode of the power output stage, a switch (24) is provided which bridges the base-emitter junction of the Darlington-pair circuit (11, 12), is closed in the event of a quick disconnection of the output stage, and is opened in the event of a voltage-limited disconnection of the output stage. A voltage divider, which consists of at least two resistors (16, 18) and bridges the switching junction of the Darlington-pair circuit (11, 12), is connected by means of its pick-off to the junction point between the switch (24) and the base of the Darlington-pair circuit (11, 12), the switch (24) being connected in parallel with a part (18) of the voltage divider.

Abstract: A biasing device which is in thermal contact with an RF device for actively biasing the RF device operating in quasi-linear modes. The biasing device provides a low impedance current source with high current capability to the base of the RF device. The biasing device includes three specially-processed transistors. The second and third transistors are connected such that their base-emitter and base-collector junctions are in parallel effectively forming two exceptionally low turn on series diodes. The result of reducing the resistances of the second and third transistors, by configuration and processing, is that they turn on slightly before the RF device is biased to its quiescent point.

Abstract: When plural emitter follower cascaded transistors are employed as a buffer to drive a capacitive load wherein instabilities can occur. The capacitive loads can result in either ringing or oscillation within such a buffer. The invention relates to applying negative feedback around one or more emitter followers in the cascade. In the preferred embodiment a three stage cascade of emitter followers is employed with negative feedback connected around the penultimate stage.

Abstract: In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.

Abstract: A resistor (16) is connected in parallel with the base-emitter section of the power transistor (12) of a Darlington circuit (10-12) to detect a line interruption in its load circuit. Furthermore, circuit components (17) are provided, which are able to be controlled through the voltage dropping across the resistor (16) and which are able to be transformed into a second circuit state characterizing a line interruption when this voltage drops below a specifiable value. In this manner, through the application of a few simple and inexpensive components, a line interruption can be reliably detected in the load circuit without the use of a measuring resistor.

Abstract: An active deassertion circuit is a device that prevents signal lines used with a communications protocol from drawing too much current. Thus, the device prevents the driver(s) of the signal lines from malfunctioning and/or being damaged. The active deassertion circuit is comprised of a voltage regulator, with peripheral connections, coupled to a transistor that is used to sink excess current. The function of these elements ensures that no asserted signal line draws too much current if another signal line is actively deasserted. A method of using the active deassertion circuit is also disclosed.