Abstract: A method and apparatus for receiving reduced voltage swing signals is disclosed. A first amplifier may generate a first intermediate signal based on a difference between voltage levels of a first and second input signals, and a second amplifier may generate a second intermediate signal based on a difference in the voltage levels between the second and first input signals. A regenerative amplifier may increase a difference in the voltage level of the first and second intermediate signals using regenerative feedback and the voltage levels of the first and second input signals. A latch circuit may generate first and second output signals using the first and second intermediate signals.

Abstract: An overvoltage recovery circuit (ORC), a controller for an HVAC system and an HVAC system are disclosed herein. In one embodiment, the ORC includes: (1) a first supply voltage terminal connected to a first voltage supply, (2) a second supply voltage terminal connected to a second voltage supply, (3) interruption circuitry including a switch and a trip terminal connected to the second supply voltage terminal and (4) detection circuitry connected to the first supply voltage terminal and the switch of the interruption circuitry, the detection circuitry configured to operate the switch in response to an overvoltage condition at the first supply voltage terminal.

Abstract: This invention discloses a voltage boost circuit which comprise at least one capacitor with a first terminal connected to an output of the voltage boost circuit, a controllable switch connected between a second terminal of the capacitor and a voltage source, the second terminal being different from the first terminal, and a voltage level detector detecting the output voltage level of the voltage boost circuit and providing a control signal to the controllable switch, wherein when the output voltage exceeds a predetermined level the controllable switch is off, and when the output voltage is lower than the predetermined level the controllable switch is on.

Abstract: A common-mode feedback circuit includes an amplifying circuit, a biasing circuit connected with the amplifying circuit, and a feedback loop connecting the amplifying circuit with the biasing circuit. The feedback loop includes a first field effect transistor M1, a eighth field effect transistor M1B connected with the first field effect transistor M1, a tenth field effect transistor M2B and an eleventh field effect transistor MFB connecting the eighth field effect transistor M1B and the tenth field effect transistor M2B. The common-mode voltage value of the common-mode feedback circuit is adjusted by the eleventh field effect transistor MFB. The common-mode feedback circuit has the simple structure and is capable of achieving the common-mode feedback without the peripheral feedback circuit and the input reference voltage.

Abstract: A power interface circuit of a contact integrated circuit (IC) card reader is provided.

Abstract: A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

Abstract: A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively.

Abstract: A buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an input/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: An integrated circuit includes a monitor node adapted to receive a monitored signal. The integrated circuit also includes a multi-purpose node. The integrated circuit is adapted to receive and store a threshold presented at the multi-purpose node during a first time period. The integrated circuit is also adapted to output a fault signal from the multi-purpose node at a time after the predetermined time period. The fault signal is indicative of a relationship between the monitored signal and the threshold. With this arrangement, the multi-purpose node achieves at least two functions.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level

Abstract: A transmitter pre-driver utilizing discrete-time charge sharing between multiple capacitors to create intermediate voltages. The intermediate voltages are fed into an output driver to produce Class AB and Class A output current flow.

Abstract: A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor.

Abstract: A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

Abstract: Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The threshold voltages are determined by extrapolation from the (high) gate to source voltage. Each of the N-channel transistors is paired with a corresponding P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage equal to the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: A resistor programmable temperature switch for indicating that a preselected trip temperature has been reached includes first and second bipolar trasistors of like polarity having a fixed ratio of emitter areas; means for connecting the emitters of the first and second transistors to a common terminal; first and second current sources for providing first and second predetermined currents to the collector of the first and second transistors, respectively; a third transistor; means connecting its control terminal to the first current source and a first load terminal connected to the base of the first transistor for operating the first transistor to conduct the first predetermined current from the current source; means for interconnecting a second load terminal of the third transistor with a power supply terminal; a resistor network including first and second resistors connected between the base of the first transistor and the common terminal for biasing the base of the second transistor to a fraction of the bas

Abstract: A high current driver (100) for driving a high current load (110) in an electronic device powered by a battery (112) comprises a voltage reference (104) for generating a reference voltage, and a drive current controller (102, 302) responsive to a drive control signal for selectively switching the drive current controller (102, 302) from an active state for supplying current to the high current load (110), to an-inactive state for inhibiting the supply of current to the high current load (110). The drive current controller (102, 302) further controls the amount of current supplied to the high current load (110) when the battery (112) terminal voltage is substantially equal to the reference voltage. A load control element (108) is coupled to the drive current controller (102, 302) and drives the high current load (110) when the drive current controller (102, 302) is in the active state.

Abstract: An electronic circuit for providing a momentary switch closure function output in response to operation of a control-request switch input to a closed condition and maintenance of the control-request switch input in closed condition for an amount of time greater than the time of the momentary switch closure function output. One use of the invention is as a single switch PTO enabler in conjunction with an electronically controlled internal combustion engine to provide a required momentary switch closure input to the engine electronic control for enabling the engine speed to change to a demanded speed.

Abstract: A high input impedance common-emitter amplifier stage is disclosed. This amplifier stage utilizes a transistor to buffer the base drive from the input stage of a Darlington circuit. This buffer action increases the input impedance of the common-emitter stage by a factor of beta (.beta.) of the buffering transistor. Various embodiments are disclosed.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: In order to drive an MOS field-effect transistor as a voltage interrupter in a DC/DC converter operating on the chopper principle, a suitable circuit arrangement has an input transistor (T1) for current control on the input side with a low voltage change, a downstream phase reversing transistor (T2) and a complementary stage formed from a first and a second further transistor (T3, T4) whose collectors are interconnected. An auxiliary voltage is applied which is raised to the input voltage to be regulated. The complementary stage switches without any overlap by means of different current switching thresholds for the first further transistor (T3) and the phase reversing transistor (T2) which drives the second further transistor (T4). In addition, it switches with a switch-on delay, so that the switched-on duration of an upstream switched-mode regulator chip can be increased to 100%. The internal current consumption of the circuit arrangement is in this case low.

Abstract: A voltage input circuit for providing an output in response to an input signal. According to a preferred embodiment of the invention, an output having a first state and a second state is generated. The output is switched from the first state to the second state when a capacitor is charged for a first predetermined time period by the input signal having a magnitude greater than a first predetermined threshold magnitude. The capacitor is disabled to prevent the output from switching from the first state to the second state if the input signal falls below the first predetermined threshold magnitude during the first time period. The output is switched from the second state to the first state when the input signal has a magnitude less than a second predetermined threshold magnitude for a second predetermined time period.

Abstract: An amplifier circuit (10) is provided. Amplifier (10) has an amplifier stage (14) that is coupled to control an output stage (18). Output stage (18) includes a sourcing circuit (20) and a sinking circuit (22). Output stage (18) also includes a mirror circuit (42) that is coupled to an output of amplifier stage (14). Output stage (18) also includes a current balancing circuit (30) coupled to mirroring circuit (42) and sourcing circuit (20). Mirroring circuit (42) draws current from balancing circuit (30) in response to a first predetermined output from amplifier stage (14) such that balancing circuit (30) causes an insignificant current to flow in sourcing circuit (20). Thus amplifier (10) operates to sink current from an external load (12). Alternatively, mirroring circuit (42) may draw an insignificant current from balancing circuit (30) in response to a second predetermined output of the amplifier stage (14). This causes a significant current flow in sourcing circuit (20).

Abstract: An impedance converter includes an emitter follower constructed of a first transistor with a first resistor connected between an emitter electrode of the first transistor and an output terminal. Input to the emitter follower is provided by a second transistor of complementary type, with input signal applied to the base of the second transistor and the emitter electrode of the second transistor coupled to the base of the first transistor with a second resistor. Bias current in the second transistor and second resistor is in constant proportion to bias current in the first transistor and first resistor. Output impedance can be made positive, negative or zero by appropriate proportioning of the first and second resistors.

Abstract: A circuit for sensing the current delivered to a load, or multiple loads, such presented by a polyphase DC motor, without significantly dissipating the energy delivered to the load, has a predriver circuit and a power delivery circuit for each load. The predriver circuit is connected in a series path between a voltage source and a control element of the power delivery circuit, and the power delivery circuit is connected between a connection node and a respective one of the loads. A sensing element is connected in a series path between the source of voltage and the power delivery circuit connection node. In a preferred embodiment, the sensing element is a resistor, the predriver circuit is a PNP transistor, and the power delivery circuit is an NPN transistor. The PNP and NPN transistors are connected to form a pseudo-Darlington transistor pair, with the collectors of the NPN transistors interconnected to enable a single sense resistor to be used to sense the current in each of the loads.