Multiple Emitter Transistor Patents (Class 327/577)
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Patent number: 10587355Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.Type: GrantFiled: January 4, 2017Date of Patent: March 10, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
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Patent number: 8581660Abstract: A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor.Type: GrantFiled: April 24, 2012Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Ubol Udompanyavit, Osvaldo Jorge Lopez, Joseph Maurice Khayat
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Patent number: 6144252Abstract: A plurality of heterojunction bipolar transistors (HBTs), each including one or more HBT cells, are combined so as to drive all of the cells equally and involves coupling the input drive signal via a pair of microstrip transmission lines to the two farthest transistors having a first common circuit node therebetween. A third microstrip transmission line is located between the other two microstrip transmission lines and is connected from the first circuit node to a second circuit node which is common to the two nearer transistors in order to couple the drive signal in an opposite direction to the nearer transistors. In such an arrangement, a negative mutual inductance exists between the center transmission line and the two outer transmission lines. The microstrip transmission lines are designed with physical dimensions and mutual separation distances so that the total inductance of the transmission lines which exists between the circuit nodes equals the mutual inductance be therebetween.Type: GrantFiled: May 6, 1997Date of Patent: November 7, 2000Assignee: Northrop Grumman CorporationInventors: Mike L. Salib, John J. Zingaro
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Patent number: 5438296Abstract: A multiplier circuit includes first and second squaring circuits each having a differential input terminal pair. A first input terminal of the differential input terminal pair of the first squaring circuit is applied with a first input voltage and the second input terminal thereof is applied with a second input voltage opposite in phase to the first input voltage. A first input terminal of the differential input terminal pair of the second squaring circuit is supplied with the second input voltage and the second input terminal thereof is applied with the first input voltage. The first and second squaring circuits each includes two sets of unbalanced differential transistor pairs which are arranged so that their inputs are opposite in phase and their outputs are connected in common. The transistors of each unbalanced differential transistor pair have different emitter sizes.Type: GrantFiled: July 22, 1994Date of Patent: August 1, 1995Assignee: NEC CorporationInventor: Katsuji Kimura
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Patent number: 5408141Abstract: An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).Type: GrantFiled: January 4, 1993Date of Patent: April 18, 1995Assignee: Texas Instruments IncorporatedInventors: Joseph A. Devore, Ross E. Teggatz, Konrad Wagensohner
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Patent number: 5396117Abstract: By disposing various current-sensing layers on a semiconductor element with a current-sensing function, wherein signals corresponding to the sensing currents derived from each current-sensing electrode are inputted independently into said over-current control circuit and short-circuit control circuit in a control circuit for said semiconductor element; or by constructing the current-sensing resistor in said control circuit with various resistors connected in series, wherein a single sensing current flows into this resistor to generate various detection voltages divided by the resistor, while detection voltages with different values are inputted independently into said main current turn-off command circuit and main current control circuit the value I.sub.oc of the over-current detection level for the semiconductor element with a current-sensing function and the value I.sub.sct at the short-circuit current detection level can be set independently of each other. Therefore, while increasing I.sub.oc, setting I.Type: GrantFiled: November 23, 1993Date of Patent: March 7, 1995Assignee: Fuji Electric Co., Ltd.Inventors: Toru Housen, Manabu Watanabe
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Patent number: 5387813Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.Type: GrantFiled: December 14, 1992Date of Patent: February 7, 1995Assignee: National Semiconductor CorporationInventors: Ali A. Iranmanesh, David E. Bien, Michael J. Grubisich