Abstract: A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor.

Abstract: A sharp transition is achieved between pushing and pulling an output current by simultaneously diverting the bias current from a series stacked transistor circuit and from the base of a sink transistor. After the series stacked transistor circuit is kept from conducting output current, the sink transistor allows bias current to drive the other transistor circuit in the stack. Each of the transistor circuits in the stack is associated with a bias current and a sink transistor. The sink transistors and the bottom transistor circuit in the stack have emitters coupled to a floating ground. A switching signal input circuit includes an input transistor and a current mirror. The low input signal from the switching signal input circuit to a control input at a first sink transistor in the drive circuit is clamped relative to the floating ground.

Abstract: A compensation circuit provides a compensation current to a node of an integrated circuit that experiences increased reverse-bias leakage current between a n-type leaking epitaxial region and a p-type substrate with increased temperature. The compensation circuit includes a p-type substrate, a n-type compensator epitaxial region, an contact region, a center p-type region and a plurality of peripheral p-type regions. The peripheral p-type regions function as either a node collector or a reference collector. The compensation current is substantially determined by the ratio of the total peripheral surface area facing the center p-type region associated with the node collector and the total peripheral surface area facing the center p-type region associated with the reference collector and is also determined by the total surface area of the n-type compensator epitaxial region.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A stackable voltage comparator circuit that may be used in an analog voltage address decoder circuit for performing voltage window comparisons. The voltage comparator circuit includes a plurality of voltage comparator circuit cells, each of which includes a differential input stage made up of a pair of transistors which receives a current source. A first comparator circuit cell includes a differential input pair of transistors with one of the transistors having a first collector and a second collector, with the second collector being coupled to an output line. The first comparator circuit cell compares an input window with a first threshold voltage and produces an output at the output line. A second comparator circuit cell compares the input voltage with a second threshold voltage and includes a second differential input pair of transistors.

Abstract: A subcircuit for discharging a capacitor at a preselected rate incorporates a first transistor and a second transistor connected with the emitter of the first transistor providing current to the collector of the second transistor. The base of the first transistor is connected to a capacitor to be discharged at a preselected rate. The base current of the first transistor discharges the capacitor as a function of the base current provided to the second transistor. In order to provide a current of very small magnitude to the base of the second transistor, a plurality of lateral PNP transistors are connected in a plural stage arrangement in order to take advantage of the current dividing characteristic of lateral PNP transistors. A collector of one lateral PNP transistor is connected to the emitter of another so that each stage of the subcircuit reduces the output current by a very precise ratio.