Minority Carrier Storage Patents (Class 327/579)
  • Patent number: 9154125
    Abstract: A method is disclosed for controlling an IGBT component and a gate driver. An exemplary method includes producing, with two separate driver circuits, a gate voltage for controlling the IGBT component, the outputs of the driver circuits being connected to free ends of a series connection of resistive components. A location, such as a midpoint between the series connection, forms the gate voltage.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 6, 2015
    Assignee: ABB TECHNOLOGY OY
    Inventor: Leo Nuutinen
  • Patent number: 7402862
    Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: July 22, 2008
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Yang-Kyu Choi, Hyunjin Lee
  • Patent number: 5532629
    Abstract: A track and hold circuit including an input terminal V.sub.IN, a first node, a second node and a capacitor C.sub.H. A diode D connects between the first node and the input terminal V.sub.H. Circuitry coupled to the first node makes the diode conductive during track mode of operation, indicated by a clock CK being at a first state, and non-conductive during hold mode of operation, indicated by a clock CK being at a second state. A transistor Q3 is coupled between said first node and said second node. The capacitor C.sub.H is connected to said second node. The transistor Q3 is operative to charge the capacitor C.sub.H during track mode and to isolate the capacitor C.sub.H from the input terminal V.sub.IN during hold mode. Additional circuitry coupled to said transistor Q3 senses the clock shifting from said first to said second state to rapidly discharge the inherent base/emitter capacitor of the transistor Q3 to thereby cause rapid turn off of the transistor Q3.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: July 2, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Krishnasawamy Nagaraj
  • Patent number: 5477185
    Abstract: An integrated circuit which includes a detection circuit for detecting the condition of saturation of an output transistor (Q.sub.0) whose collector-emitter path is intended to pass an output current. A threshold circuit (A) of the detection circuit is arranged to perform a switching operation when a representative parameter of the condition of saturation crosses a given threshold. A control transistor (Q) is arranged to supply at least a part of the base current of the output transistor (Q.sub.0) and the threshold circuit (A) performs its switching operation when the value of the current passing through the collector-emitter path of the control transistor exceeds a given level.
    Type: Grant
    Filed: October 19, 1993
    Date of Patent: December 19, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Philippe B. E. Jouen
  • Patent number: 5448190
    Abstract: A voltage-to-current conversion circuit is disclosed which includes a MOS transistor of a source-grounded type having a gate connected to an input terminal, an output circuit producing an output current at an output terminal in response to a drain current of the transistor, and a control circuit maintaining the drain voltage of the transistor to such a value that has the transistor operates in a non-saturation (triode) region.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: September 5, 1995
    Assignee: NEC Corporation
    Inventor: Toshiyuki Etoh