Abstract: An interface circuit for a position sensor system including an oscillator generating an oscillation signal having a carrier frequency and a primary phase, a primary coil responsive to the oscillation signal, and a secondary coil electromagnetically coupled to the primary coil by a target and configured to generate a secondary signal having the carrier frequency and a secondary phase provides phase compensation.

Abstract: A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Abstract: A system and method for detection of an event and recording data associated with the event. An application-specific integrated circuit (ASIC) for event-driven data acquisition from detector is disclosed. The event-driven circuitry stays silent when there is no event detected on the detector. The event-driven data acquisition system consumes small power and may consume no memory during waiting for an event. Once the event arrives (e.g. photons, particle or ion hits the detector panel), the event is detected and recorded. The ASIC includes multi-channel ADCs (or ADC arrays) with flexible resolution which enables an option to operate at a lower resolution during the silent period to save power.

Abstract: The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.

Abstract: An envelope tracking supply modulator includes an amplifier circuit and a zero peaking circuit. The amplifier circuit receives an envelope input, generates a modulated supply voltage according to the envelope input, and provides the modulated supply voltage to a power amplifier. The zero peaking circuit is coupled to the amplifier circuit, and applies zero peaking to the amplifier circuit, where the zero peaking inserts a zero at a frequency.

Abstract: A single-photon detection method and apparatus. The single-photon detection method detects a single photon using a single-photon detection apparatus, and includes generating an output signal through a photon detector by receiving a light signal as an input, generating a negative voltage comparison result through a negative voltage comparator by receiving the output signal as an input, and generating a photon detection result based on the negative voltage comparison result.

Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absol

Abstract: An operational amplifier with totem pole connected output transistors having inputs coupled to multiplexers for selectable coupling of signals and voltage levels thereto. The high and low output transistors may be forced hard on or hard off in addition to normal coupling of signals thereto. The operation of the output transistors may be dynamically changed to pass only positive going signals, negative going signals, placed in a tristate high impedance state, hard connected to a supply voltage and/or hard connected to supply common return. A core independent peripheral (CIP) may also be coupled to the operational amplifier for dynamically changing the multiplexer inputs in real time, as can external control signals to a control circuit coupled to the multiplexers.

Abstract: A method, computer system, and computer program product for determining head wear of magnetic tape head elements of tape drives during operation. The method may include receiving a first calibration parameter for a first tape head element at a first time. Calibration parameter for the first tape head element may be compared with a reference parameter. Determination may be made whether to remove the first tape head element from service or generate a warning, based on a result of the comparison. Method may include generating the first calibration parameter by calculating midpoint bias voltage for the first tape head element as a function of bias current and head resistance. The first calibration parameter for the first tape head element may be bias current parameter or bias resistance parameter. The first calibration parameter for the first tape head element may be less than, equal to, or greater than the reference parameter.

Abstract: A system for detection of a target sound in an environment of a vehicle, includes an audio sensor, a computer processor, and a memory storing a digital target sound template produced by converting a sample of the target sound in accordance with conversion parameters. The computer processor receives a sound signal from the audio sensor, digitizes the sound signal in accordance with the conversion parameters, and determines a degree of similarity between the digitized signal and the digital target sound template. The sound signal may be logarithmically amplified before being digitized. The sound signal may be received from two audio sensors, and the direction of the target sound may be determined based on a difference between time indices for detection of the target sound for each audio sensor.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control switching of a sampling circuit. An example apparatus includes an offset window detector to determine whether a first voltage meets a first threshold of a target input voltage; a settling time detector coupled to the offset window detector, the settling time detector to determine whether a second voltage meets a second threshold, the second voltage dependent on a delay of the settling time detector, the delay of the settling time detector to track a time response of a scaling amplifier; and a sample acquisition controller coupled to the offset window detector and the settling time detector, the sample acquisition controller operable to cause a reference voltage to be sampled, in response to the first threshold and the second threshold being met.

Abstract: A signal detection circuit includes a signal input terminal, a rectifier circuit, a comparator circuit; a current source, and a comparator output terminal. The rectifier circuit is coupled to the signal input terminal and is configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit is coupled to the rectifier circuit and is configured to receive a common mode signal and to generate a difference current based on a difference of the common mode signal and the rectified signal. The current source is coupled to the comparator circuit and is configured to generate a reference current. The comparator output terminal is configured to provide an output signal based on a difference of the reference current and the difference current.

Abstract: Technologies are provided for preventing transmission of cyclic redundancy check (CRC) errors, and/or other errors, within a computer network that uses cut-through forwarding of network packets. For example, counts of CRC errors can be maintained for network packets processed by network devices. When a CRC error condition is detected based on the counts of CRC errors, cut-through forwarding is disabled on at least a portion of the network (e.g., on one or more specific network ports and/or on one or more specific network devices). While cut-through forwarding is disabled, the affected portion of the network uses store-and-forward for processing network packets. When the CRC error condition no longer exists, then cut-through forwarding is re-enabled on the portion of the network.

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

Abstract: A capacitance-to-voltage conversion circuit including a variable capacitance element, an integration circuit, and first and second sample and hold circuits. Capacitance value of the variable capacitance element varies depending on a physical quantity. The integration circuit outputs a voltage as a result of integration. The first sample and hold circuit samples and holds the voltage. The second sample and hold circuit samples and holds the sampled voltage and performs a simultaneous sampling operation in synchronism with the first sample and hold circuit at the same period as at least an initial sampling period. The second sample and hold circuit performs a sampling operation at a rear-end period in a sampling period of the first sample and hold circuit other than the sampling period.

Abstract: A peak hold circuit configured for use in a downhole sensor includes a long tail pair circuit, a correction circuit, and a current mirror circuit. The current mirror circuit includes two current mirrors connected to a long tail pair formed by a first transistor and a second transistor. The current mirror also includes a first resistor and a second resistor connected to a third transistor. The first transistor is connected to a correction transistor of the correction circuit. The value of the first resistor is selected to be essentially equal to the same value as the second resistor so that when the long tail pair is balanced, the current flowing through a collector of the second transistor is equal to the current flowing through the first transistor, causing the correction transistor to switch off.

Abstract: The present disclosure is directed to a high power factor quasi resonant converter. The converter converts an AC power line input to a DC output to power a load, generally a string of LEDs. The power input is fed into a transformer being controlled by a power switch. The power switch is driven by a controller having a shaping circuit. The shaping circuit uses a current generator, switched resistor and capacitor to produce a sinusoidal reference voltage signal. The controller drives the power switch based on the voltage reference signal, resulting in a sinusoidal input current in a primary winding of the transformer, resulting in high power factor and low total harmonic distortion for the converter.

Abstract: A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes a first node providing a voltage indicative of the amplitude voltage. The first node is in series with each of the first pair of transistors. The circuit includes a compensation circuit. The compensation circuit includes a second pair of transistors configured in parallel and a second node. The second node is coupled in series with each transistor of the second pair. The circuit includes an amplifier including a first amplifier input coupled to the first node and a second amplifier input coupled to the second node.

Abstract: An RF peak-detector circuit can operate over a wide range and can compensate or correct an output voltage error term that depends on the thermal voltage and the input signal voltage. At or near a minimum value of the input signal voltage range, such compensation can include a scaled base-emitter ratioing of bipolar junction transistors used to generate the output voltage, each of which can be biased by a primary current. At or near a maximum value of the input signal voltage range, this can include using an auxiliary bias current circuit that can shift auxiliary bias current between these bipolar junction transistors. The auxiliary bias current circuit can include scaled bipolar junction transistors in a cross-coupled configuration and an equivalent resistance circuit between emitters of the cross-coupled BJTs. This can provide a robust approach for improving the accuracy of an RF peak-detector circuit over a wide range.

Abstract: A peak detector circuit comprises a first output coupled to ground by a first load and to emitter terminals of first and second switching devices. A second output is coupled to ground by a second load and to emitter terminals of third and fourth switching devices. A third output is coupled to a supply voltage node by a third load and to collector terminals of the first and second switching devices. A fourth output is coupled to the supply voltage node by a fourth load and to collector terminals of the third and fourth switching devices. The first, second, third, and fourth switching devices have control terminals which are biased with a common bias voltage. The first, second, third and fourth load are selected so that R1=R2=?f*R3=?f*R4, with R1, R2, R3, R4 being a resistance of the first, second, third and fourth loads, respectively, and ?f a common-base current gain of the switching devices.

Abstract: A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor.

Abstract: A system and method for controlling the output power of a heat source. The system includes a user interface so that a user may select the power required from the heat source, a power supply, and a controller that receives a rectified signal having a work ratio that corresponds to a nominal voltage of an alternating voltage signal corresponding to a phase of a power supply. The controller is configured to control the output power of the heat source in accordance with the power selected by the user, and modifies, if necessary, the work cycle of a power signal linked to the heat source in accordance with the work ratio in order to compensate possible differences in the nominal voltage between different power supplier.

Abstract: A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.

Abstract: A near field communications (NFC) device is disclosed that detects an envelope of a radio frequency (RF) signal. The NFC device includes a peak detector that determines the envelope of the RF signal. The peak detector compares a first differential signal voltage to a second differential signal voltage. The peak detector delays a rising edge of a first differential signal and provides the first differential signal voltage to the peak detector output when the first differential signal voltage is greater than the second differential signal voltage. The peak detector delays a falling edge of a second differential signal and provides the second differential signal voltage to the peak detector output when the second differential signal voltage is greater than the first differential signal voltage.

Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.

Abstract: By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacitance using a mathematical formula.

Abstract: An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

Abstract: A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal is valid.

Abstract: A detection circuit includes a differential circuit including a pair of differential transistors configured to receive the input differential signal and a first current source, the pair of the differential transistors having a common output terminal connected to the first current source, a hold capacitor connected between the common output terminal and a reference potential for generating a hold potential, a level sensing circuit configured to sense a voltage level of the input differential signal and output a switching signal, and a switch configured to receive the switching signal and electrically connect the common output terminal and a second current source when the switching signal exceeds a threshold level being lower than the hold potential by a predetermined amount, and electrically disconnect the common output terminal and the second current source when the switching signal stays lower than the threshold level.

Abstract: A differentiator generates a time derivative signal from a time-variable signal. A transconductance amplifier generates a biasing control signal as a function of the time derivative signal. A supply network functions to supply the differentiator and transconductance amplifier. The supply network is driven by the biasing control signal output from the transconductance amplifier. With this configuration, speed of operation of the differentiator and transconductance amplifier vary with the supply provided by the supply network, and the supply is modulated as a function of the received time-variable signal.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: A circuit can include multiple data input ports and data output ports, pickoff tees coupled therebetween, and a resistive network coupled between the pickoff tees. A differential signal generator can be coupled with the resistive network and the pickoff tees. Resistances of the pickoff tees and resistive network can be selected such that impedances looking into the data input ports and data output ports are matched to a desired system impedance.

Abstract: An oscillator and the control method thereof. The oscillator includes an oscillation unit to receive a first current and to generate an oscillating signal according to the first current, a frequency-to-voltage converter to receive the oscillating signal and to generate a converted voltage according to a frequency of the oscillating signal, and a voltage-to-current converter to receive the converted voltage and to generate the first current according to the converted voltage, wherein the first current is modulated from a first value to a second value after the initiation of the oscillation unit.

Abstract: The invention provides a linear burst mode receiver comprising a first amplifier connected to a photodiode adapted to detect an optical input burst signal, a second amplifier connected to said photodiode; and means for deriving the peak input current of the detected burst signal using said second amplifier. The invention further provides means for using the derived peak input current to adjust the gain of the first amplifier during the preamble of each burst, such that the output voltage swing of the first amplifier equals a given reference, independent of the strength of the optical input burst signal. The usage of the fast feed-forward automatic gain control mechanism solves the problems with gain switching and non-linearity prevalent in today's burst-mode receivers.

Abstract: A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a plurality of frames. Each frame is then further divided into a plurality of smaller blocks, and the signal peak is determined in each block individually followed by selecting the peak signal value from the said blocks.

Abstract: An activity detector for a differential signal formed by two components may include a current source connected to a power supply line, and a first transistor has a drain being powered by the current source, and has a source that forms a first input terminal receiving a first component of the differential signal. A second transistor has a drain being powered by the current source, and has a source forms a second input terminal receiving the second component of the differential signal. A bias circuit applies a potential to the gates of the first and second transistors, establishing a balance condition where all the current from the current source is distributed between the two transistors when the first and second input terminal potential is equal to a threshold value. An activity indication terminal is taken from the drains of the first and second transistors.

Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: Circuits and methods for fast detection of a low voltage in the range of few ?Volts have been achieved. In a preferred embodiment the low voltage represents a current via a shunt resistor and the circuit is used to generate a digital wake-up signal. In regard of the wake-up application the circuit invented is activated periodically and in case of a certain level of the voltage drop, e.g. 50 ?V, at the shunt resistor. The time required for a measurement of the voltage drop is inclusive calibration and integration time far below 1 ms. It is obvious that the circuit invented can be used for any measurements of very small voltages.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.

Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.

Abstract: An apparatus and a method for processing a signal, and for estimating a point corresponding to a maximum slope from an envelope of an input signal, are provided. A signal processing apparatus includes an envelope detecting unit configured to detect an envelope of an input signal. The signal processing apparatus further includes a correcting unit configured to correct slopes, each of the slopes being between respective points of the envelope, based on information on a clipping interval of the envelope. The signal processing apparatus further includes an estimating unit configured to estimate a point, of the envelope, in which a corrected slope, among the corrected slopes, includes a maximum value.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input.

Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.

Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.

Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.

Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.

Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.

Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

Abstract: A method of maximum power point tracking for a photovoltaic module system is disclosed. The photovoltaic module system may comprise a photovoltaic module array comprising a plurality of identical photovoltaic modules, and the tracking method may comprise: detecting system parameters and environmental parameters of the photovoltaic module array; estimating a first voltage coefficient of one photovoltaic module according to the system parameters and the environmental parameters; estimating a plurality of second voltage coefficients of the photovoltaic module array according to the first voltage coefficient with different shading ratios; estimating a plurality of local maximum power point powers according to corresponding second voltage coefficients; and determining a whole maximum power point by comparing the local maximum power point powers with one another.