Abstract: A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

Abstract: A conversion circuit and an adapter that resolve a voltage drop problem of a power supply of a driver in an ACF circuit. The conversion circuit includes an active clamp flyback circuit, a drive circuit, and a replenishment power transistor. The active clamp flyback circuit is configured to perform power conversion. The drive circuit is configured to output a drive signal and a reference voltage. The drive signal is used to drive the active clamp flyback circuit. A first terminal of the replenishment power transistor is coupled to an input terminal of the active clamp flyback circuit, a second terminal of the replenishment power transistor is coupled to a power supply terminal of the drive circuit, and a gate of the replenishment power transistor is configured to receive the reference voltage.

Abstract: A sensing circuit includes: a comparison circuit for comparing an input signal to a corresponding limit threshold; and a control circuit for periodically selecting the limit threshold and sampling a comparison result to execute an interval determination step, thus determining an interval of the input signal. The interval determination step includes steps S100 and S200. Step S100: when the input signal is higher than an ascending upper limit threshold for consecutive plural times, assigning a higher adjacent interval as a following interval; when the input signal is lower than a descending lower limit threshold for consecutive plural times, assigning a lower adjacent interval as a following interval; and executing the interval determination step corresponding to the following interval. Step S200: When no adjacent interval is assigned as the following interval, generating an interval output signal corresponding to the interval and entering the corresponding step S100.

Abstract: An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.

Abstract: A comparator is disclosed. The comparator has a power input terminal used to input electricity, a first and a second to-be-compared voltage input terminal used to receive the first and second to-be-compared voltage, an offset voltage adjusting circuit used to adjust an offset voltage, a comparative circuit used to compare the first to-be-compared voltage and a third to-be-compared voltage which is a sum of the second to-be-compared voltage and the offset voltage and to generate a comparative result, and a comparative result output terminal used to output the comparative result.

Abstract: A differential output buffer includes first and third switches and second and fourth switches which are connected in series respectively between a first voltage source and a current source, and a replica circuit includes a second voltage source which is equivalent to a first voltage source. A current control circuit controls a current flowing to the current source in such a manner that a voltage of a third node between two resistive elements connected in series between a first node between the first and third switches and a second node between the second and fourth switches and having an equal resistance value is equal to a reference voltage, for example, and a voltage control circuit generates a control signal in such a manner that a voltage of any node excluding an output terminal of the second voltage source in the current path is equal to a second reference voltage.

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

Abstract: Differential voltage mode signal driver circuitry is presented in which a differential current mode amplifier input stage provides a differential signal, and an output stage includes a pair of bipolar transistors receiving the differential signal and being connected in series with a pair of cross-coupled field effect transistors that are coupled to corresponding current sources, where a negative impedance circuit is connected between the field effect transistors to substantially cancel a parasitic capacitance of a driven output circuit.

Abstract: Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.

Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.

Abstract: Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.

Abstract: A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.

Abstract: A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage.

Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.

Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Abstract: A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N?1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2? radians or a multiple thereof, where N is greater than 1.

Abstract: A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents.

Abstract: A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage.

Abstract: According to a novel aspect, operating an analog rail-to-rail comparator circuit with common mode detection of differential input signals includes generating a hysteresis current for the comparator circuit based on a common mode voltage used for the common mode detection. The hysteresis current is added to a differential output of a comparator in the comparator circuit, such that a hysteresis voltage at an output of the comparator circuit is substantially independent of the common mode voltage.

Abstract: Apparatus and methods provide a differential current buffer. The current buffer has cross-coupled feedback and offers relatively good common-mode rejection and a relatively low and linear input impedance, which can reduce intermodulation distortion. The current buffer can be used in, for example, an RF modulator, such as a quadrature modulator.

Abstract: A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function.

Abstract: A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner.

Abstract: Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.

Abstract: Example methods and apparatus to adjust control loop timing in a process control system are disclosed. A disclosed example method includes receiving a first input signal generated via a first process control device within a process control system, determining within the process control system if the first input signal is received during a first scheduled time period of a control loop, and adjusting within the process control system a timing of a subsequent input signal received from the first process control device to cause the subsequent input signal to be received during a subsequent scheduled time period of the control loop, wherein the timing of the subsequent input signal is based on at least when the first input signal was received.

Abstract: A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.

Abstract: A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes.

Abstract: An inverter is configured by double gate TFTs, and an inverter is configured by double gate TFTs. Top gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(+), and bottom gate terminals are connected to an output of the inverter and an output terminal OUT. Bottom gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(?), and bottom gate terminals are connected to an output of the inverter. With this, threshold voltages of the inverters are controlled so as to facilitate switching operations of the inverters, and whereby the comparator circuit operates at a high speed. It is possible to obtain a comparator circuit that is insusceptible to a variation in the threshold voltages of the transistors and fluctuation of a common mode voltage of an input signal and capable of operating at a high speed.

Abstract: An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal.

Abstract: This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.

Abstract: A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state (0 or 1) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor. The ratio of latch intrinsic capacitance and the capacitance of the sampling capacitor can be adjusted to trim hysteresis value. The hysteresis function does not require additional capacitors or additional logic.

Abstract: A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: There is provided a PWM comparator which needs no current detecting differential amplifier in a control circuit constituting a current mode control DC/DC converter. The comparator includes a differential input stage including two pairs of input differential transistors whose sources are commonly connected for each pair; two constant-current sources connected to the common sources of the pairs of input differential transistors, respectively; a load transistor commonly connected to drain sides of the pairs and performing a current-voltage conversion; and an output stage connected to a point where the differential input stage and the load transistor are connected to each other. A feedback voltage of an output voltage and a slope compensating waveform signal are input to terminals, respectively, of one pair, and voltages at both ends of a current detecting resistor, which is connected in series to the inductor, are input to terminals, respectively, of the other pair.

Abstract: A method and apparatus provide an IP telephone or similar device with a mechanism to receive and at least briefly loop back discovery signals received from a telecommunications device such as an Ethernet switch while not permitting the loop back of data packet signals. No mechanical relays are required and the circuitry can be fully integrated on an integrated circuit using commonly available techniques, if desired.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: An alternating-current (AC) coupling integrated circuit (IC) suppresses signal errors introduced by a steady-state input signal. The IC includes an operational amplifier, a true direct-current (DC) bias network, a complimentary DC-bias network and first and second feedback elements. The operational amplifier has an inverting input, a non-inverting input and an output. The true DC-bias network has first and second branches that are coupled to one another and the non-inverting input. The complimentary DC-bias network has third and fourth branches that are coupled to one another and the inverting input. First and second feedback elements generate first and second control signals in response to a characteristic of one of the true input signal and the complimentary input signal. The control signals prevent the voltage at the inputs to the operational amplifier from reaching an equivalent, steady-state, DC-bias voltage.

Abstract: A comparator circuit. A comparator circuit may include a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node and/or output a resultant voltage, and/or a current source to supply a first bias current to a first node and/or supply a second bias current to a second node. A comparator may include a first bias switch to bias a current flowing from a first node to a ground voltage source, a second bias switch to bias a part of a current flowing from a second node to a ground voltage source, a third bias switch to bias a remaining part of a current flowing from a second node to a ground voltage source, and/or a bias converting unit to supply a third bias current to a second node.

Abstract: Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.

Abstract: A rail-rail comparator having an input stage with independent positive and negative differential voltage offset compensation tracks changes in Gm (transconductance) of the input stage. By tracking the changes in Gm (transconductance) of the input stage, hysteresis of the rail-rail comparator becomes insensitive to the input common mode voltage. A two-stage rail-rail comparator may be used for adding hysteresis to a second stage. The first stage of the two-stage rail-rail comparator operates at substantially unity gain. The second stage of the two-stage rail-rail comparator operates as a regular high gain amplifier with hysteresis. Additional circuitry tracks the Gm (transconductance) change of the first stage to make the second stage hysteresis insensitive to the input common mode voltage at the first stage. This also makes it easier to create a programmable hysteresis that is accurate over all input voltage values.

Abstract: An amplifier includes: an operation amplifier including a positive input terminal and a negative input terminal; and a detector which detects that a difference between a voltage of the positive input terminal and a voltage of the negative input terminal is equal to or exceeds a predetermined value and outputs a detection signal.

Abstract: An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.