Abstract: A protection relay comprises a digital processing unit including: a first filter to eliminate a DC component in the time-series data, the first filter having a first window length; a second filter to eliminate a DC component in the time-series data, the second filter having a second window length shorter than the first window length; and a coefficient calculation unit to multiply an amplitude value of an output signal of the first filter and an amplitude value of an output signal of the second filter by first and second coefficients respectively, and integrate multiplication results. An operation determination is performed based on an output of the coefficient calculation unit. The first coefficient is decreased and the second coefficient is increased when a failure of the power system is detected, and thereafter, the first coefficient and the second coefficient are changed with a lapse of time.

Abstract: A circuit for generating a bias voltage for a terminating end capacitor in a controller area network (CAN) bus having a CANH and a CANL terminals is disclosed. The circuit includes a configurable voltage source, a controller to generate a control signal to operate the configurable voltage source, a CANH error detector and a CANL error detector. The CANH error detector and the CANL error detector are configured to provide inputs to the controller. The controller is configured to generate the control signal based on the outputs of the CANH error detector and the CANL error detector. The configurable voltage source is configured to output a bias voltage based on the control signal.

Abstract: Embodiments relate to a light-emitting-diode (LED) cell that includes a LED and a controller. The controller receives a brightness data signal and generates a driving signal corresponding to the brightness data signal. The controller includes a comparator that receives the brightness data signal and a control waveform signal. The controller is coupled to a switched current source that generates a driving current based on the driving signal.

Abstract: The invention relates to a heat cycle machine which operates according to the Stirling cycle and can be used as a multi-valent stand-alone power supply for households (electricity and heat), that is to say using various energy sources (sunlight, combustion of present materials). The heat cycle machine comprises at least one hot oil connection (4, 5) that can be connected to any desired heat source, at least one cold water connection (6, 7) and two chambers (2) that contain a working gas. The chambers (2) are connected to one another via at least one working gas line (18, 20) in which is integrated a working rotor (13) that can be driven by the working gas which is alternately heated in one of the chambers (2) and cooled in the other chamber (2).

Abstract: A charging circuit includes a power path control unit which switches a first switch connected between a system connection terminal and a battery connection terminal on while not charging, and switches the first switch on and a second switch connected between an external power supply input terminal and the system connection terminal on while charging so as to supply power to a system and charge a battery. A voltage difference between the external power supply input terminal and the battery connection terminal is detected, a current flowing between the external power supply input terminal and the system connection terminal is detected, and it is determined that an external power supply is disconnected based on the detection results of the voltage differences and the current.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a first signal and a second signal; generating a first digital count corresponding to a characteristic of the first signal; subsequent to generating the first digital count, generating a second digital count corresponding to a characteristic of the second signal; and comparing the first digital count with the second digital count. Other embodiments are also described and claimed.

Abstract: The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Abstract: A circuit for preventing a setup fail between a first latch and a second latch according to one embodiment of the present invention comprises a mimic combinational logic module and a clock compare module. The mimic combinational logic module is configured to receive a first clock signal for the first latch and to generate a delayed first clock signal, which is a delayed version of the first clock signal. The clock compare module is configured to provide a delayed second clock signal, which is a delayed version of a second clock signal for the second latch, to the second latch after receiving the delayed first clock signal and the second clock signal.

Abstract: An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals.

Abstract: Methods and apparatus to control power in a printer are disclosed. An example apparatus includes a first field effect transistor having a first terminal, a second terminal, and a third terminal, the second terminal coupled with a first voltage input. The example apparatus further includes a second field effect transistor having a fourth terminal, a fifth terminal, and a sixth terminal, the fourth terminal coupled with the first terminal of the first field effect transistor, the fifth terminal coupled with a second voltage input. The example apparatus further includes a first comparator having a first input coupled to the first input voltage, having a second input coupled to the second input voltage, and having an output coupled with the third terminal.

Abstract: A measuring device for triggering a test signal with a superposed noise signal includes a trigger unit, which is connected to a recording unit, where the test signal with respectively superposed noise signal is supplied to both. The trigger unit outputs a trigger signal to the recording unit as soon as the test signal with superposed noise signal has completely run through a hysteresis range. The trigger unit is connected to a hysteresis adjustment unit, where the hysteresis adjustment unit specifies a hysteresis range to the trigger unit, and where the hysteresis range specified by the hysteresis adjustment unit is adjustable.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

Abstract: Peak power reduction in transmit chains of multi-band radiocommunication devices is performed. By using knowledge of the phase transformations which occur at the upconverter to determine how baseband signal samples will combine at the higher (upconverted) frequency, peak prediction and corresponding baseband signal modification can be performed in a way that reduces peak power of the combined signal.

Abstract: A semiconductor integrated circuit including: a data input circuit inputting a data input signal from outside and outputting the signal; a comparison value register memorizing an expectation value of the output signal varying in accordance with an input to the data input circuit; and a comparing circuit comparing a value in accordance with a switching number of the output signal of the data input circuit and the expectation value, is provided.

Abstract: An improved fast settling bit slicing comparator circuit includes a comparator having a non-inverting and inverting input; the non-inverting input receiving an input signal; a filter circuit for receiving the input signal and being connected with the inverting input of the comparator; a positive feedback circuit interconnected between the output of the comparator and the non-inverting input of the comparator for introducing a predetermined hysteresis offset; the filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of the hysteresis offset. Additionally, the positive feedback circuit may be interconnected with the inverting input of the comparator through the filter circuit for gradually reducing the effect of the hysteresis offset by reducing the differential voltage between the inverting and non-inverting inputs.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: A method of determining the quality of a sensed signal has capturing, comparing, categorizing, and a decision-making steps. The capturing step is used to capture a plurality of signals. A magnitude of each of the plurality of signals is compared to a predetermined value to determine a relationship between each of the plurality of signals to the predetermined value. A result of each comparison is categorized according to one of a plurality of predetermined criteria. The categorizing step is repeated at least until a predetermined number of results has been reached in at least one of the plurality of predetermined criteria. A decision is made based on which of the plurality of predetermined criteria reaches the predetermined number.

Abstract: A digital storage oscilloscope employs an improved edge triggering circuit that discards some of trigger events when it determines that there are many more trigger events than the oscilloscope can use. The determination is made in response to detection of a characteristic of the signal that indicates a repetitive nature of a complex signal. Certain trigger events are selected to be acted upon, and others are discarded, in response to the determination. The circuitry dynamically reacts to changes in the input signal in response to detection of different criteria for a characteristic of repetition as the input signal changes.

Abstract: According to one embodiment, there is provided an optocoupler system configured to generate current signals having high, low and no amplitude portions in response to the receipt of logic high and low input signals. The varying amplitude portions of the current signals are used to drive other portions of the isolation circuitry, and result in reduced power consumption and dissipation, as well as reduced pulse width distortion.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values.

Abstract: A latched comparator circuit (1) comprises an input amplification unit (10), a buffer unit (20), and a control unit (30). The input amplification unit (10) comprises a first and a second input terminal (40a, 40b) for receiving a first and a second input voltage, respectively, of the latched comparator circuit (1). The input amplification unit (10) further comprises a first and a second output terminal (50a, 50b) for outputting a first and a second output voltage, respectively, of the input amplification unit (10). In addition, the input amplification unit (10) comprises a reset terminal (60) arranged to receive a reset signal for resetting the input amplification unit. The buffer unit (20) is operatively connected to the first and the second output terminal (50a, 50b) of the input amplification unit (10). Furthermore, the buffer unit (20) comprises a first and a second output terminal (70a, 70b) for outputting a first and a second output voltage, respectively, of the buffer unit (20).

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: A vending machine door switch interface allows multiple controllers, including the vending machine controller, to employ a single door switch without polarization or interference. The interface includes a comparator having inputs coupled across the door switch and, based on the door switch state, produces an output signal indicating whether the service door is closed or open. The comparator output when the service door is known to be open is recorded to subsequently distinguish open and closed states. Unbalanced connections to power and ground result in different voltages at the comparator inputs when the door switch is closed.

Abstract: An improved fast settling bit slicing comparator circuit includes a comparator having a non-inverting and inverting input; the non-inverting input receiving an input signal; a filter circuit for receiving the input signal and being connected with the inverting input of the comparator; a positive feedback circuit interconnected between the output of the comparator and the non-inverting input of the comparator for introducing a predetermined hysteresis offset; the filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of the hysteresis offset. Additionally, the positive feedback circuit may be interconnected with the inverting input of the comparator through the filter circuit for gradually reducing the effect of the hysteresis offset by reducing the differential voltage between the inverting and non-inverting inputs.

Abstract: The differential drive circuit generates a differential drive signal having a root mean square value defined by a digital input value. The differential drive signal includes a first differential component and a second differential component. The circuit comprises a first differential component generator and a second differential component generator. The first differential component generator is for counting the clock signal to generate successive values of a periodic count. Each of the values includes a most-significant bit. The first differential component generator is additionally for generating the first differential component in response to successive ones of the most-significant bit of the count. The second differential component generator is for generating the second differential component in response to the digital input value and the successive values of the count.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: In a semiconductor device, a monitoring circuit monitors and detects a quantity of noise in the semiconductor device. A control circuit has capacitances and controls connections to the capacitances such a decoupling capacitance value provided between a first power supply and a second power supply is dynamically adjusted based on the detected noise quantity.

Abstract: High-side switch arrangement having a switching transistor, the collector of which is connected to a battery connection of the high-side switch arrangement and the emitter of which is connected to an output connection of the high-side switch arrangement, an actuating transistor, the emitter of which is connected to the battery connection of the high-side switch arrangement and the collector of which is connected to the base of the switching transistor, and a diagnosis transistor, the emitter of which is connected to the battery connection of the high-side switch arrangement and the collector of which is connected to the output connection of the high-side switch arrangement, wherein the diagnosis transistor has a saturation collector for sensing the saturation current of the diagnosis transistor.

Abstract: A circuitry comprises a comparator for comparing a signal received on a first input to a signal received on a second input. A control register associated with the first multiplexer stores control values enabling connection of one input of the first multiplexer to the output of the first multiplexer.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

Abstract: The differential drive circuit generates a differential drive signal having a root mean square value defined by a digital input value. The differential drive signal includes a first differential component and a second differential component. The circuit comprises a first differential component generator and a second differential component generator. The first differential component generator is for counting the clock signal to generate successive values of a periodic count. Each of the values includes a most-significant bit. The first differential component generator is additionally for generating the first differential component in response to successive ones of the most-significant bit of the count. The second differential component generator is for generating the second differential component in response to the digital input value and the successive values of the count.

Abstract: A stable, low power consumption signal detecting circuit may include: a delay circuit, which receives a base clock signal and generates multiple versions thereof having time delay relationships thereto, respectively; dual amplifiers, which detect valid ones of input signals by comparing the input signals with reference voltage signals in response to the multiple versions of the base clock signal, respectively; a combining unit, which generates a combination signal in response to output signals of the dual amplifiers; and a sampling circuit, which samples the combination signal according to the base clock signal and generates an output signal.

Abstract: A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount which is larger than the first delay amount, and a plurality of timing comparators for sampling a plurality of data signals delayed by the plural stages of first variable delay elements by the strobe signal delayed by the second variable delay element of the same stage, wherein the timing comparator includes a dynamic D-FF circuit for latching and outputting the data signal by its parasitic capacitance based on the strobe signal, a buffer for delaying the strobe signal, and a positive feed-back D-FF circuit for latching and outputting the output signal outputted by the dynamic D-FF circuit by its positive feed-back circuit based on the strobe signal delayed.

Abstract: A technique for reducing input currents associated with a comparator circuit during certain events includes minimizing bias currents associated with the comparator circuit when a magnitude of an input signal at a signal input of the comparator circuit is a predetermined value from a magnitude of a reference signal applied to a reference input of the comparator circuit. The bias currents are increased when the magnitude of the input signal is within the predetermined value of the magnitude of the reference signal.

Abstract: Device for reducing the lag and the dark current of a particle detector, and in particular a photon detector.

Abstract: In a signal read circuit including a plurality of circuit rows each having a charge amplifier connected to a photoelectric conversion element PD and a CDS circuit 2S for performing correlated double sampling for an output from the charge amplifier, a dummy circuit row DMY having the same configuration as a circuit row SLT is connected in parallel with this circuit row SLT. By calculating the difference between these circuit rows connected in parallel, offset variations generated in the two circuit rows SLT and DMY can be removed.

Abstract: A driving circuit includes a level shift circuit that shifts and outputs the level of the main signals consisting of the “ON” and “OFF” signals that respectively instruct ON and OFF of the power device, a transmitter circuit that latches the main signals to transmit to the power device, a mask signal circuit that generates a mask signal based on the main signals to prevent the transmission of the main signals when the logic of the “ON” and “OFF” signals becomes the same to cause false operation, a potential difference adding circuit that gives a potential difference &Dgr;V between a signal as the main signal input to the mask signal circuit and a signal as the main signal input to the transmitter circuit.

Abstract: A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second transistor (M2) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M3) and a fourth transistor (M4) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as those used in RFID transponders.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed