Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.

Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Abstract: The sampling of a signal is described using a sampling bridge, the sampling terminals of which are interconnected.

Abstract: A compact optically-pumped solid-state laser designed for efficient nonlinear intracavity frequency conversion into desired wavelengths using periodically poled nonlinear crystals. These crystals contain dopants such as MgO or ZnO and/or have a specified degree of stoichiometry that ensures high reliability. The laser includes a solid-state gain media chip, such as Nd:YVO4, which also provides polarization control of the laser; and a periodically poled nonlinear crystal chip such as PPMgOLN or PPZnOLT for efficient frequency doubling of the fundamental infrared laser beam into the visible wavelength range. The described designs are especially advantageous for obtaining low-cost green and blue laser sources. Also described design of the continuously operated laser with an electro-optic element for modulation of the intensity of the laser output at frequencies up to hundred of megahertz. Such modulation is desired for various applications, including compact projectors with high resolution.

Abstract: Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Abstract: A packaged controller for closed-loop control applications includes two dies packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.

Abstract: Circuitry includes a pre-amplifier having a differential output, where the differential output corresponds to a common mode voltage; a multiplexer including sets of transistors, each of which has a control input; a comparator including input terminals, a first terminal of the input terminals to receive a signal that is based on an output of the multiplexer, and a second terminal of the input terminals to receive a threshold voltage; a compensation circuit to produce a divided voltage that varies in accordance with variations in the common mode voltage; and an amplifier to receive a predefined voltage and to use the divided voltage to affect the predefined voltage to produce the threshold voltage for the comparator. Signals in the differential output of the pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

Abstract: A packaged controller for closed-loop control applications includes two dice packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.

Abstract: A method and an arrangement are provided for balancing the switching transient behavior of parallel connected power semiconductor components. The method includes providing a switch signal to the parallel connected power semiconductor components for changing the state of the components, forming control signals for each of the parallel connected components from the switch signal, and determining, during the change of state of the power semiconductor component, the voltage induced to an inductance in the main current path of the component in each of the parallel connected components. The method also includes comparing each of the induced voltages with a predetermined threshold voltage, measuring time differences between the time instants at which the induced voltages crosses the threshold voltage, and modifying one or more of the control signals on the basis of the measured time differences in the respective following state change for balancing the switching transient behavior.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.

Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.

Abstract: A switched-mode level-shifter shifts a differential voltage superimposed on a common-mode voltage. In the level shifter, a common-mode inductive reactor has at least two windings, and at least one of the differential voltage and the common-mode voltage are applied to at least one of the windings of the reactor. A switch charges the inductive reactor when caused to be in a first state, where the inductive reactor when charged experiences a change of flux according to the applied voltage. The switch also actuates a reset of the charged inductive reactor when caused to be in a second state, where the inductive reactor when reset reverses the change of flux experienced thereby. A source of a chopping signal is provided to alternately drive the switch between the first and second states, where each of the first and second states is one of in and out of conduction.

Abstract: Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.

Abstract: An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog storage circuit includes a sample and hold circuit including an amplifier having first and second inputs and a switch coupled to the first input of the amplifier. The switch includes a first switching device forming a core of the switch, a second switching device coupled to the first switching device to disconnect the first switching device from a first terminal during the hold phase, and a third switching device coupled to the first switching device to connect the first switching device to a second terminal during the hold phase to minimize accumulation mode conduction in the first switching device.

Abstract: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.

Abstract: Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate.

Abstract: A method and apparatus for optically clocked optoelectronic track and hold (“OCOETH”) device. The OCOETH device includes a diode bridge, input node, at least two current sources and at least two photodetectors. The input node is operatively coupled to the diode bridge and can receive an analog input signal. The at least two current sources are operatively coupled to the diode bridge and can forward bias the diode bridge. The at least two photodetectors are operatively coupled to the diode bridge and can receive an optical input clocking signal, and can reverse bias and forward bias the diode bridge in response to the optical input clocking signal. The hold capacitor is operatively coupled to the diode bridge and can track the analog input signal when the diode bridge is forward biased, and can hold the analog input signal when the diode bridge switches from forward biased to reverse biased.

Abstract: A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.

Abstract: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A wavelength tunable mode-locked laser system including a complex laser cavity comprising a broadband reflective mirror at one end and a wavelength chirped selective mirror at the other end. The system further includes a gain element and a low finesse Fabry-Perot etalon element inside the laser cavity. The gain element may be a semiconductor laser chip, with a broadband high reflection coating at one end and a partially reflecting coating at its other end. The gain element has a well-defined length, such that its longitudinal modes match a required optical frequency grid. The system also includes an active modulation element applied externally on said complex laser cavity to provide mode-locking of a specific cavity length among said defined predetermined cavity lengths, such that all possible optical frequencies emitted by the laser system are stabilized to the linear grid dictated by the Fabry-Perot longitudinal modes, that could be in accordance with the International Telecommunications Union Standards.

Abstract: A switched capacitor circuit having an integrator, a switch, a capacitor, a field effect transistor, and a network. The switch is connected to the integrator. The capacitor is connected to the switch. The field effect transistor is connected to the capacitor. The network is connected to a gate terminal of the field effect transistor. The network is configured to control a resistance of the field effect transistor in response to variations in an input signal voltage received at the field effect transistor.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A sample and hold circuit that is coupled to a control voltage source and a signal source has a sampling bridge coupled in series between a first resonant tunneling diode. The bridge comprises a plurality of diodes. The sampling bridge couples an input voltage signal that is to be sampled to a holding capacitor when the sampling bridge is forward biased. The bridge substantially decouples the input voltage signal from the holding capacitor when the sampling bridge diodes are reversed biased. The resonant tunneling diodes when reversed biased allow the bridge to be isolated from the control voltage source to allow the holding capacitor to float at the sampled value of the input voltage.

Abstract: To form a high-speed, high-precision sample hold circuit with the minimum number of elements and low current consumption, there is provided a sample hold circuit including an operational amplifier including differential input stage in which sources or emitters are commonly connected, a cascode current mirror circuit for receiving a differential output from the different input stage, and a push-pull output stage having a diamond circuit connected to the cascode current mirror circuit, wherein a hold capacitor is connected to the output of the operational amplifier, and the push-pull output stage is switched between a buffer operation mode and a high-impedance output operation mode in accordance with a logic signal.

Abstract: In a sample/hold circuit, a current switch generates a constant current in response to a control signal. A first current mirror circuit receives the constant current to generate first and second currents, and a second current mirror circuit receives the first current to generate a third current. A voltage buffer receives an input voltage at an input terminal to generate an output voltage at an output terminal. The voltage buffer is activated by the second and third currents. A hold capacitor is connected to the output terminal.

Abstract: A low distortion track-and-hold circuit in which a simple, four-transistor amplifier makes the circuit characteristics independent of the source impedance, and compensates for unequal voltage drops caused by mismatched diodes. An additional pair of bipolar transistors is used to eliminate errors caused by switching transients coupled through the diodes. In the track mode, the differential output voltage between two sampling capacitors tracks the differential input voltage of the circuit. At the end of the track time, this differential output voltage is equal to the differential input voltage. During the hold period, the sampling capacitors are isolated from the differential input voltage. The voltages controlling the switching diodes reverse symmetrically during the transition from track to hold, resulting in a cancellation of any feedthrough of the switching transients to the sampling capacitor. Beta and temperature compensation circuits are also included in the differential track-and-hold circuit.

Abstract: The signals to be measured are transformed in the system to discrete time digital signals by synchronous sampling. These digital signals are then processed by a digital signal processor for vector detection and for computing digital feedback sent to the sampling gates. The analyzer has improved characteristics in the area of linearity, drift and test port signal injection because of its highly optimized architecture based on synchronous sampling with digital feedback. It possesses unique characteristics such as the ability to tune to a harmonic or a subharmonic of the excitation frequency and a good sensitivity in a high impedance environment.

Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator.